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RISC-V_Desk_Mat.html
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RISC-V_Desk_Mat.html
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<!DOCTYPE html>
<html>
<head>
<title>RISC-V Reference Sheet</title>
<link rel="stylesheet" href="https://cdnjs.cloudflare.com/ajax/libs/normalize/8.0.1/normalize.min.css" integrity="sha512-NhSC1YmyruXifcj/KFRWoC561YpHpc5Jtzgvbuzx5VozKpWvQ+4nXhPdFgmx8xqexRcpAglTj9sIBWINXa8x5w==" crossorigin="anonymous" referrerpolicy="no-referrer" />
<link href="https://fonts.googleapis.com/css?family=Titillium+Web&display=swap" rel="stylesheet">
<style>
.page {
background: #222;
color: #FFF;
height: 300mm;
width: 800mm;
font-family: "Titillium Web", sans-serif;
font-weight: normal;
font-size: 2.8mm;
}
.flex {
display: flex;
}
.flex.vertical {
flex-direction: column;
}
.flex.gap {
gap: 4mm;
}
table {
width: 100%;
}
table, th, td {
border: 0.5px solid #666;
border-collapse: collapse;
}
th, td {
padding: 0.6mm 1mm;
}
@media print {
body {
margin: 0;
}
@page {
size: 80cm 30cm;
orientation: landscape;
}
}
.content {
margin: 0 8mm;
}
th {
height: 8mm;
font-weight: normal;
font-size: 4mm;
}
.header > img {
height: 18mm;
}
.header > span {
font-size: 7mm;
line-height: 18mm;
margin-left: 2mm
}
</style>
</head>
<body>
<!-- Original Image: https://www.kindpng.com/imgv/TomTJxJ_cute-angry-anime-girl-hd-png-download/ -->
<img src="assets/corner.png" style="position: absolute; top: 200mm; left: 700mm; height: 100mm">
<div class="page">
<div class="content vertical flex">
<div class="header flex">
<img src="assets/riscv-logo-1.png">
<span>
Reference Sheet
</span>
</div>
<div class="gap flex">
<div class="vertical gap flex">
<div class="gap flex">
<div>
<!-- Integer Register -->
<table>
<tr>
<th colspan="4" style="background: #5c6bc0">General registers</th>
</tr>
<tr>
<td>Register</td>
<td>ABI Name</td>
<td>Description</td>
<td>Saver</td>
</tr>
<tr>
<td>x0</td>
<td>zero</td>
<td>Constant zero</td>
<td>--</td>
</tr>
<tr>
<td>x1</td>
<td>ra</td>
<td>Return address</td>
<td>Caller</td>
</tr>
<tr>
<td>x2</td>
<td>sp</td>
<td>Stack pointer</td>
<td>Callee</td>
</tr>
<tr>
<td>x3</td>
<td>gp</td>
<td>Global pointer</td>
<td>--</td>
</tr>
<tr>
<td>x4</td>
<td>tp</td>
<td>Thread pointer</td>
<td>--</td>
</tr>
<tr>
<td>x5</td>
<td>t0</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x6</td>
<td>t1</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x7</td>
<td>t2</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x8</td>
<td>s0/fp</td>
<td>Saved register / Frame pointer</td>
<td>Callee</td>
</tr>
<tr>
<td>x9</td>
<td>s1</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x10</td>
<td>a0</td>
<td>Function argument / Return value</td>
<td>Caller</td>
</tr>
<tr>
<td>x11</td>
<td>a1</td>
<td>Function argument / Return value</td>
<td>Caller</td>
</tr>
<tr>
<td>x12</td>
<td>a2</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x13</td>
<td>a3</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x14</td>
<td>a4</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x15</td>
<td>a5</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x16</td>
<td>a6</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x17</td>
<td>a7</td>
<td>Function argument</td>
<td>Caller</td>
</tr>
<tr>
<td>x18</td>
<td>s2</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x19</td>
<td>s3</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x20</td>
<td>s4</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x21</td>
<td>s5</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x22</td>
<td>s6</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x23</td>
<td>s7</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x24</td>
<td>s8</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x25</td>
<td>s9</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x26</td>
<td>s10</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x27</td>
<td>s11</td>
<td>Saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>x28</td>
<td>t3</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x29</td>
<td>t4</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x30</td>
<td>t5</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>x31</td>
<td>t6</td>
<td>Temporary</td>
<td>Caller</td>
</tr>
</table>
</div>
<div>
<!-- FP Register -->
<table>
<tr>
<th colspan="4" style="background: #ff7043">Floating Point Registers</th>
</tr>
<tr>
<td>Register</td>
<td>ABI Name</td>
<td>Description</td>
<td>Saver</td>
</tr>
<tr>
<td>f0</td>
<td>ft0</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f1</td>
<td>ft1</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f2</td>
<td>ft2</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f3</td>
<td>ft3</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f4</td>
<td>ft4</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f5</td>
<td>ft5</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f6</td>
<td>ft6</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f7</td>
<td>ft7</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f8</td>
<td>fs0</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f9</td>
<td>fs1</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f10</td>
<td>fa0</td>
<td>FP argument / Return value</td>
<td>Caller</td>
</tr>
<tr>
<td>f11</td>
<td>fa1</td>
<td>FP argument / Return value</td>
<td>Caller</td>
</tr>
<tr>
<td>f12</td>
<td>fa2</td>
<td>FP argument</td>
<td>Caller</td>
</tr>
<tr>
<td>f13</td>
<td>fa3</td>
<td>FP argument</td>
<td>Caller</td>
</tr>
<tr>
<td>f14</td>
<td>fa4</td>
<td>FP argument</td>
<td>Caller</td>
</tr>
<tr>
<td>f15</td>
<td>fa5</td>
<td>FP argument</td>
<td>Caller</td>
</tr>
<tr>
<td>f16</td>
<td>fa6</td>
<td>FP argument</td>
<tr>
<td>f17</td>
<td>fa7</td>
<td>FP argument</td>
<td>Caller</td>
</tr>
<tr>
<td>f18</td>
<td>fs2</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f19</td>
<td>fs3</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f20</td>
<td>fs4</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f21</td>
<td>fs5</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f22</td>
<td>fs6</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f23</td>
<td>fs7</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f24</td>
<td>fs8</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f25</td>
<td>fs9</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f26</td>
<td>fs10</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f27</td>
<td>fs11</td>
<td>FP saved register</td>
<td>Callee</td>
</tr>
<tr>
<td>f28</td>
<td>ft8</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f29</td>
<td>ft9</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f30</td>
<td>ft10</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
<tr>
<td>f31</td>
<td>ft11</td>
<td>FP temporary</td>
<td>Caller</td>
</tr>
</table>
</div>
<div>
<!-- Assembler Directives -->
<table>
<tr>
<th colspan="4" style="background: #757575">Assembler Directives</th>
</tr>
<tr>
<td>Directive</td>
<td style="width: 40mm">Arguments</td>
<td>Description</td>
</tr>
<tr>
<td>.align</td>
<td>integer</td>
<td>align to power of 2 (alias for .p2align)</td>
</tr>
<tr>
<td>.file</td>
<td>"filename"</td>
<td>emit filename FILE LOCAL symbol table</td>
</tr>
<tr>
<td>.globl</td>
<td>symbol_name</td>
<td>emit symbol_name to symbol table (scope GLOBAL)</td>
</tr>
<tr>
<td>.local</td>
<td>symbol_name</td>
<td>emit symbol_name to symbol table (scope LOCAL)</td>
</tr>
<tr>
<td>.common</td>
<td>symbol_name,size,align</td>
<td>emit common object to .bss section</td>
</tr>
<tr>
<td>.ident</td>
<td>"string"</td>
<td>accepted for source compatibility</td>
</tr>
<tr>
<td>.section</td>
<td>[{.text,.data,.rodata,.bss}]</td>
<td>emit section (if not present, default .text) and make current</td>
</tr>
<tr>
<td>.size</td>
<td>symbol, symbol</td>
<td>accepted for source compatibility</td>
</tr>
<tr>
<td>.text</td>
<td></td>
<td>emit .text section (if not present) and make current</td>
</tr>
<tr>
<td>.data</td>
<td></td>
<td>emit .data section (if not present) and make current</td>
</tr>
<tr>
<td>.rodata</td>
<td></td>
<td>emit .rodata section (if not present) and make current</td>
</tr>
<tr>
<td>.bss</td>
<td></td>
<td>emit .bss section (if not present) and make current</td>
</tr>
<tr>
<td>.string</td>
<td>"string"</td>
<td>emit string</td>
</tr>
<tr>
<td>.asciz</td>
<td>"string"</td>
<td>emit string (alias for .string)</td>
</tr>
<tr>
<td>.equ</td>
<td>name, value</td>
<td>constant definition</td>
</tr>
<tr>
<td>.macro</td>
<td>name arg1 [, argn]</td>
<td>begin macro definition \argname to substitute</td>
</tr>
<tr>
<td>.endm</td>
<td></td>
<td>end macro definition</td>
</tr>
<tr>
<td>.type</td>
<td>symbol, @function</td>
<td>accepted for source compatibility</td>
</tr>
<tr>
<td>.option</td>
<td>{arch, rvc, norvc, pic, nopic, relax, norelax, push, pop}</td>
<td>RISC-V options</td>
</tr>
<tr>
<td>.byte</td>
<td>expression [, expression]*</td>
<td>8-bit comma separated words</td>
</tr>
<tr>
<td>.2byte</td>
<td>expression [, expression]*</td>
<td>16-bit comma separated words</td>
</tr>
<tr>
<td>.4byte</td>
<td>expression [, expression]*</td>
<td>32-bit comma separated words</td>
</tr>
<tr>
<td>.word</td>
<td>expression [, expression]*</td>
<td>32-bit comma separated words</td>
</tr>
<tr>
<td>.8byte</td>
<td>expression [, expression]*</td>
<td>64-bit comma separated words</td>
</tr>
<tr>
<td>.dword</td>
<td>expression [, expression]*</td>
<td>64-bit comma separated words</td>
</tr>
<tr>
<td>.dtprelword</td>
<td>expression [, expression]*</td>
<td>32-bit thread local word</td>
</tr>
<tr>
<td>.dtpreldword</td>
<td>expression [, expression]*</td>
<td>64-bit thread local word</td>
</tr>
<tr>
<td>.sleb128</td>
<td>expression</td>
<td>signed little endian base 128, DWARF</td>
</tr>
<tr>
<td>.uleb128</td>
<td>expression</td>
<td>unsigned little endian base 128, DWARF</td>
</tr>
<tr>
<td>.p2align</td>
<td>p2,[pad_val=0],max</td>
<td>align to power of 2</td>
</tr>
<tr>
<td>.balign</td>
<td>b,[pad_val=0]</td>
<td>byte align</td>
</tr>
<tr>
<td>.zero</td>
<td>integer</td>
<td>zero bytes</td>
</tr>
<tr>
<td>.variant_cc</td>
<td>symbol_name</td>
<td>annotate the symbol with variant calling convention</td>
</tr>
<tr>
<td>.attribute</td>
<td>name, value</td>
<td>RISC-V object attributes</td>
</tr>
</table>
</div>
</div>
<div class="gap flex">
<!-- CSR Registers -->
<table>
<tr>
<th colspan="8" style="background: #7e57c2">CSR Registers (Partial List)</th>
</tr>
<tr>
<td>Number</td>
<td>Privilege</td>
<td>Name</td>
<td>Description</td>
<td>Number</td>
<td>Privilege</td>
<td>Name</td>
<td>Description</td>
</tr>
<tr>
<td>0x001</td>
<td>URW</td>
<td>fflags</td>
<td>Floating-Point Accrued Exceptions</td>
<td>0x300</td>
<td>MRW</td>
<td>mstatus</td>
<td>Machine status register</td>
</tr>
<tr>
<td>0x002</td>
<td>URW</td>
<td>frm</td>
<td>Floating-Point Dynamic Rounding Mode</td>
<td>0x301</td>
<td>MRW</td>
<td>misa</td>
<td>ISA and extensions</td>
</tr>
<tr>
<td>0x003</td>
<td>URW</td>
<td>fcsr</td>
<td>Floating-Point Control and Status Register</td>
<td>0x302</td>
<td>MRW</td>
<td>medeleg</td>
<td>Machine exception delegation register</td>
</tr>
<tr>
<td>0xC00</td>
<td>URO</td>
<td>cycle</td>
<td>Cycle counter for RDCYCLE instruction</td>
<td>0x302</td>
<td>MRW</td>
<td>mideleg</td>
<td>Machine interrupt delegation register</td>
</tr>
<tr>
<td>0xC01</td>
<td>URO</td>
<td>time</td>
<td>Timer for RDTIME instruction</td>
<td>0x304</td>
<td>MRW</td>
<td>mie</td>
<td>Machine interrupt-enable register</td>
</tr>
<tr>
<td>0xC02</td>
<td>URO</td>
<td>instret</td>
<td>Instructions-retired counter for RDINSTRET instruction</td>
<td>0x305</td>
<td>MRW</td>
<td>mtvec</td>
<td>Machine trap-handler base address</td>
</tr>
<tr>
<td>0xC80</td>
<td>URO</td>
<td>cycleh</td>
<td>Upper 32 bits of cycle, RV32 only</td>
<td>0x306</td>
<td>MRW</td>
<td>mcounteren</td>
<td>Machine counter enable</td>
</tr>
<tr>
<td>0xC81</td>
<td>URO</td>
<td>timeh</td>
<td>Upper 32 bits of time, RV32 only</td>
<td>0x341</td>
<td>MRW</td>
<td>mepc</td>
<td>Machine exception program counter</td>
</tr>
<tr>
<td>0xC82</td>
<td>URO</td>
<td>instreth</td>
<td>Upper 32 bits of instret, RV32 only</td>
<td>0x342</td>
<td>MRW</td>
<td>mcause</td>
<td>Machine trap cause</td>
</tr>
<tr>
<td>0xF11</td>
<td>MRO</td>
<td>mvendorid</td>
<td>Vendor ID</td>
<td>0x343</td>
<td>MRW</td>
<td>mtval</td>
<td>Machine bad address or instruction</td>
</tr>
<tr>
<td>0xF12</td>
<td>MRO</td>
<td>marchid</td>
<td>Architecture ID</td>
<td>0x344</td>
<td>MRW</td>
<td>mip</td>
<td>Machine interrupt pending</td>
</tr>
<tr>
<td>0xF13</td>
<td>MRO</td>
<td>mimpid</td>
<td>Implementation ID</td>
<td>0xB00</td>
<td>MRW</td>
<td>mcycle</td>
<td>Machine cycle counter</td>
</tr>
<tr>
<td>0xF14</td>
<td>MRO</td>
<td>mhartid</td>
<td>Hardware thread ID</td>
<td>0xB02</td>
<td>MRW</td>
<td>minstret</td>
<td>Machine instructions-retired counter</td>
</tr>
<tr>
<td>0xF15</td>
<td>MRO</td>
<td>mconfigptr</td>
<td>Pointer to configuration data structure</td>
</tr>
</table>
</div>
</div>
<div class="gap vertical flex">
<!-- RV32I Integer Instruction -->
<table>
<tr>
<th colspan="10" style="background: #5c6bc0">RV32I Base Integer Instruction</th>
</tr>
<tr>
<td>Inst.</td>
<td>Name</td>
<td>Type</td>
<td>Definition</td>
<td colspan="6">Fields</td>
</tr>
<tr>
<td>lui</td>
<td>Load Upper Immediate</td>
<td>U</td>
<td>R[rd] = {32'bimm[31], imm, 12'b0}</td>
<td colspan="4">imm[31:12]</td>
<td>rd</td>
<td>0110111</td>
</tr>
<tr>
<td>auipc</td>
<td>Add Upper Immediate to PC</td>
<td>U</td>
<td>R[rd] = PC + {imm, 12'b0}</td>
<td colspan="4">imm[31:12]</td>
<td>rd</td>
<td>0010111</td>
</tr>
<tr>
<td>jal</td>
<td>Jump And Link</td>
<td>J</td>
<td>R[rd] = PC + 4; PC = PC + {imm, 1'b0}</td>
<td colspan="4">imm[20|10:1|11|19:12]</td>
<td>rd</td>
<td>1101111</td>
</tr>
<tr>
<td>jalr</td>
<td>Jump And Link Register</td>
<td>I</td>
<td>R[rd] = PC + 4; PC = PC + R[rs1] + imm</td>
<td colspan="2">imm[11:0]</td>
<td>rs1</td>
<td>000</td>
<td>rd</td>
<td>1100111</td>
</tr>
<tr>
<td>beq</td>
<td>Branch EQual</td>
<td>B</td>
<td>if (R[rs1] == R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td style="width: 8mm">rs2</td>
<td style="width: 8mm">rs1</td>
<td>000</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>bne</td>
<td>Branch Not Equal</td>
<td>B</td>
<td>if (R[rs1] != R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td>rs2</td>
<td>rs1</td>
<td>001</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>blt</td>
<td>Branch Less Than</td>
<td>B</td>
<td>if (R[rs1] < R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td>rs2</td>
<td>rs1</td>
<td>100</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>bge</td>
<td>Branch Greater than or Equal</td>
<td>B</td>
<td>if (R[rs1] >= R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td>rs2</td>
<td>rs1</td>
<td>101</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>bltu</td>
<td>Branch Less Than Unsigned</td>
<td>B</td>
<td>if (R[rs1] < R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td>rs2</td>
<td>rs1</td>
<td>110</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>bgeu</td>
<td>Branch Greater than or Equal Unsigned</td>
<td>B</td>
<td>if (R[rs1] >= R[rs2]) PC = PC + {imm, 1'b0}</td>
<td>imm[12|10:5]</td>
<td>rs2</td>
<td>rs1</td>
<td>111</td>
<td>imm[4:1|11]</td>
<td>1100011</td>
</tr>
<tr>
<td>lb</td>
<td>Load Byte</td>
<td>I</td>
<td>R[rd] = {24'bM[][7], M[R[rs1]+imm][7:0]}</td>
<td colspan="2">imm[11:0]</td>
<td>rs1</td>
<td>000</td>
<td>rd</td>
<td>0000011</td>
</tr>
<tr>
<td>lh</td>
<td>Load Halfword</td>
<td>I</td>
<td>R[rd] = {16'bM[][7], M[R[rs1]+imm][15:0]}</td>
<td colspan="2">imm[11:0]</td>
<td>rs1</td>
<td>001</td>
<td>rd</td>
<td>0000011</td>
</tr>
<tr>
<td>lw</td>
<td>Load Word</td>
<td>I</td>
<td>R[rd] = M[R[rs1]+imm][31:0]</td>
<td colspan="2">imm[11:0]</td>
<td>rs1</td>
<td>010</td>
<td>rd</td>
<td>0000011</td>
</tr>
<tr>
<td>lbu</td>
<td>Load Byte Unsigned</td>
<td>I</td>
<td>R[rd] = {24'b0, M[R[rs1]+imm][7:0]}</td>
<td colspan="2">imm[11:0]</td>
<td>rs1</td>
<td>100</td>
<td>rd</td>
<td>0000011</td>
</tr>
<tr>
<td>lhu</td>
<td>Load Halfword Unsigned</td>
<td>I</td>
<td>R[rd] = {16'b0, M[R[rs1]+imm][15:0]}</td>