diff --git a/projects/ad469x_fmc/common/ad469x_ardz.txt b/projects/ad469x_fmc/common/ad469x_ardz.txt new file mode 100644 index 0000000000..7f25335437 --- /dev/null +++ b/projects/ad469x_fmc/common/ad469x_ardz.txt @@ -0,0 +1,13 @@ +# ad469x + +Pin Port Schematic_name System_top_name IOSTANDARD Termination +P3.10 CK_SCL SCL_ARD iic_eeprom_scl LVCMOS35 #N/A +P3.9 CK_SDA SDA_ARD iic_eeprom_sda LVCMOS35 #N/A +P3.6 CK_IO10 CSB_1 ad469x_spi_cs LVCMOS35 IOB TRUE +P3.5 CK_IO11 MOSI_ARD ad469x_spi_sdi LVCMOS35 IOB TRUE PULLTYPE PULLUP +P3.4 CK_IO12 MISO_ARD ad469x_spi_sdo LVCMOS35 IOB TRUE PULLTYPE PULLUP +P3.3 CK_IO13 SCKL_ARD ad469x_spi_sclk LVCMOS35 IOB TRUE +P3.2 CK_IO09 GP0_ARD ad469x_busy_alt_gp0 LVCMOS35 #N/A + +P4.7 CK_IO06 CNV_ARD ad469x_spi_cnv LVCMOS35 #N/A +P4.5 CK_IO04 RSTb_ARD ad469x_resetn LVCMOS35 #N/A \ No newline at end of file diff --git a/projects/ad469x_fmc/common/ad469x_bd.tcl b/projects/ad469x_fmc/common/ad469x_bd.tcl index 0ffe488abb..4bdf262c6c 100644 --- a/projects/ad469x_fmc/common/ad469x_bd.tcl +++ b/projects/ad469x_fmc/common/ad469x_bd.tcl @@ -9,6 +9,7 @@ set SPI_4WIRE $ad_project_params(SPI_4WIRE) puts "build parameter: SPI_4WIRE: $SPI_4WIRE" create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad469x_spi + create_bd_port -dir O ad469x_spi_cnv create_bd_port -dir I ad469x_spi_busy diff --git a/projects/ad469x_fmc/coraz7s/Makefile b/projects/ad469x_fmc/coraz7s/Makefile new file mode 100644 index 0000000000..d8b241ccf4 --- /dev/null +++ b/projects/ad469x_fmc/coraz7s/Makefile @@ -0,0 +1,28 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad469x_fmc_coraz7s + +M_DEPS += ../common/ad469x_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc +M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad469x_fmc/coraz7s/system_bd.tcl b/projects/ad469x_fmc/coraz7s/system_bd.tcl new file mode 100644 index 0000000000..40921e1a41 --- /dev/null +++ b/projects/ad469x_fmc/coraz7s/system_bd.tcl @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +# specify the spi reference clock frequency in MHz +set spi_clk_ref_frequency 160 + +# specify ADC resolution -- supported resolutions 16 bits +set adc_resolution 16 + +# specify ADC sampling rate in samples/seconds +set adc_sampling_rate 1000000 + +adi_project_files ad469x_fmc_coraz7s [list \ + "../../../library/common/ad_edge_detect.v" \ + "../../../library/util_cdc/sync_bits.v" \ +] + +source ../common/ad469x_bd.tcl + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 ad469x_iic + +ad_ip_instance axi_iic axi_ad469x_iic +ad_connect ad469x_iic axi_ad469x_iic/iic + +ad_cpu_interconnect 0x44a40000 axi_ad469x_iic + +ad_cpu_interrupt "ps-11" "mb-11" axi_ad469x_iic/iic2intc_irpt + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +set sys_cstring "SPI_CLK_FREQ=$spi_clk_ref_frequency\ +ADC_RESOLUTION=$adc_resolution\ +SAMPLING_RATE=$adc_sampling_rate" + +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad469x_fmc/coraz7s/system_constr.xdc b/projects/ad469x_fmc/coraz7s/system_constr.xdc new file mode 100644 index 0000000000..db8fc2fb74 --- /dev/null +++ b/projects/ad469x_fmc/coraz7s/system_constr.xdc @@ -0,0 +1,28 @@ +############################################################################### +## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ad4696_ardz SPI interface + +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sclk]; ## CK_IO13 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad469x_spi_sdo]; ## CK_IO12 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad469x_spi_sdi]; ## CK_IO11 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_cs]; ## CK_IO10 + +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ad469x_busy_alt_gp0]; ## CK_IO09 +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports ad469x_spi_cnv]; ## CK_IO06 +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports ad469x_resetn]; ## CK_IO04 + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_scl]; ## CK_SCL +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_sda]; ## CK_SDA + +# rename auto-generated clock for SPIEngine to spi_clk - 160MHz +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] + +# relax the SDO path to help closing timing at high frequencies +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_ad469x_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_ad469x_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] diff --git a/projects/ad469x_fmc/coraz7s/system_project.tcl b/projects/ad469x_fmc/coraz7s/system_project.tcl new file mode 100644 index 0000000000..5672939108 --- /dev/null +++ b/projects/ad469x_fmc/coraz7s/system_project.tcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_xilinx.tcl +source ../../scripts/adi_board.tcl + +# Parameter description + +# SPI_4WIRE - For 0 CNV is linked to PWM. For 1 CNV is linked to SPI_CS + +adi_project ad469x_fmc_coraz7s 0 [list \ + SPI_4WIRE [get_env_param SPI_4WIRE 0]] + +adi_project_files ad469x_fmc_coraz7s [list \ + "../../../library/common/ad_iobuf.v" \ + "../../common/coraz7s/coraz7s_system_constr.xdc" \ + "system_top.v" \ + "system_constr.xdc"] + +adi_project_run ad469x_fmc_coraz7s diff --git a/projects/ad469x_fmc/coraz7s/system_top.v b/projects/ad469x_fmc/coraz7s/system_top.v new file mode 100644 index 0000000000..e9953a89c1 --- /dev/null +++ b/projects/ad469x_fmc/coraz7s/system_top.v @@ -0,0 +1,179 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter SPI_4WIRE = 0 +) ( + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [1:0] btn, + inout [5:0] led, + + inout iic_eeprom_scl, + inout iic_eeprom_sda, + + // ad469x SPI configuration interface + + input ad469x_spi_sdi, + output ad469x_spi_sdo, + output ad469x_spi_sclk, + output ad469x_spi_cs, + output ad469x_spi_cnv, + + input ad469x_busy_alt_gp0, + inout ad469x_resetn +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire ad469x_spi_cnv_s; + wire ad469x_spi_cs_s; + + // instantiations + + assign gpio_i[63:34] = 30'b0; + + assign ad469x_spi_cnv = (SPI_4WIRE == 0) ? ad469x_spi_cnv_s : ad469x_spi_cs_s; + assign ad469x_spi_cs = ad469x_spi_cs_s; + + assign gpio_i[33] = ad469x_busy_alt_gp0; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_ad469x_iobuf ( + .dio_t(gpio_t[32]), + .dio_i(gpio_o[32]), + .dio_o(gpio_i[32]), + .dio_p(ad469x_resetn)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_buttons ( + .dio_t(gpio_t[1:0]), + .dio_i(gpio_o[1:0]), + .dio_o(gpio_i[1:0]), + .dio_p(btn)); + + ad_iobuf #( + .DATA_WIDTH(6) + ) i_iobuf_leds ( + .dio_t(gpio_t[7:2]), + .dio_i(gpio_o[7:2]), + .dio_o(gpio_i[7:2]), + .dio_p(led)); + + assign gpio_i[31:8] = gpio_o[31:8]; + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .ad469x_spi_sdo (ad469x_spi_sdo), + .ad469x_spi_sdo_t (), + .ad469x_spi_sdi (ad469x_spi_sdi), + .ad469x_spi_cs (ad469x_spi_cs_s), + .ad469x_spi_sclk (ad469x_spi_sclk), + .ad469x_spi_busy (ad469x_busy_alt_gp0), + .ad469x_spi_cnv (ad469x_spi_cnv_s), + .ad469x_iic_scl_io (iic_eeprom_scl), + .ad469x_iic_sda_io (iic_eeprom_sda), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o()); + +endmodule