diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v index 9fd4d34a647..59dd46584a1 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -51,6 +51,8 @@ module axi_dac_interpolate #( input dma_valid_b, output dma_ready_a, output dma_ready_b, + input last_a, + input last_b, input dac_enable_a, input dac_enable_b, @@ -131,7 +133,7 @@ module axi_dac_interpolate #( wire dac_correction_enable_b; wire [15:0] dac_correction_coefficient_a; wire [15:0] dac_correction_coefficient_b; - wire [19:0] trigger_config; + wire [20:0] trigger_config; wire en_start_trigger; wire en_stop_trigger; @@ -156,6 +158,7 @@ module axi_dac_interpolate #( wire [ 1:0] raw_transfer_en; wire [15:0] dac_raw_ch_a_data; wire [15:0] dac_raw_ch_b_data; + wire rearm_on_last_s; // signal name changes @@ -175,6 +178,7 @@ module axi_dac_interpolate #( assign en_trigger_pins = trigger_config[17:16]; assign en_trigger_adc = trigger_config[18]; assign en_trigger_la = trigger_config[19]; + assign rearm_on_last_s = trigger_config[20]; assign trigger_active = |trigger_config[19:16]; assign trigger = (ext_trigger & en_trigger_pins) | @@ -224,6 +228,8 @@ module axi_dac_interpolate #( .dac_int_data (dac_int_data_a), .dma_ready (dma_ready_a), .underflow (underflow_a), + .rearm_on_last (rearm_on_last_s), + .last (last_a), .filter_mask (filter_mask_a), .interpolation_ratio (interpolation_ratio_a), @@ -252,6 +258,8 @@ module axi_dac_interpolate #( .dac_valid (dac_valid_b), .dac_valid_out (dac_valid_out_b), .underflow (underflow_b), + .rearm_on_last (rearm_on_last_s), + .last (last_b), .dac_enable (dac_enable_b), .dac_int_data (dac_int_data_b), diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v index 9a20618f4d5..4d23ed22323 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v @@ -51,6 +51,9 @@ module axi_dac_interpolate_filter #( output dac_valid_out, output underflow, + input rearm_on_last, + input last, + input [ 2:0] filter_mask, input [31:0] interpolation_ratio, input [15:0] dac_correction_coefficient, @@ -105,7 +108,6 @@ module axi_dac_interpolate_filter #( wire dac_cic_valid; wire [109:0] dac_cic_data; - wire dma_valid_ch_sync; wire dma_valid_ch; wire flush_dma; @@ -114,6 +116,7 @@ module axi_dac_interpolate_filter #( wire transfer_start; wire transfer_ready; + wire rearm_channel; // Once enabled the raw value will be selected until the DMA has valid data. // This is a workaround for when DAC channels are start/stopped independent @@ -197,12 +200,13 @@ module axi_dac_interpolate_filter #( assign transfer_start = !(en_start_trigger ^ trigger) & transfer_ready & !dma_transfer_suspend; + assign rearm_channel = last & rearm_on_last; always @(posedge dac_clk) begin stop_transfer <= transfer_sm == IDLE ? 1'b0 : (stop_transfer & !clear_stop_flag) | dma_transfer_suspend | (en_stop_trigger & trigger) | - (sync_stop_channels & dma_valid & dma_valid_adjacent); + (sync_stop_channels & (dma_valid ^ dma_valid_adjacent)); end // transfer state machine @@ -224,7 +228,9 @@ module axi_dac_interpolate_filter #( TRANSFER: begin clear_stop_flag <= 1'b0; transfer <= 1'b1; - if (stop_transfer) begin + if (rearm_channel) begin + transfer_sm_next <= WAIT; + end else if (stop_transfer) begin if (flush_dma_in) begin transfer_sm_next <= FLUSHING; end else begin diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v index 65477973fa0..1c367a5854d 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v @@ -54,7 +54,7 @@ module axi_dac_interpolate_reg( output dac_correction_enable_b, output [15:0] dac_correction_coefficient_a, output [15:0] dac_correction_coefficient_b, - output [19:0] trigger_config, + output [20:0] trigger_config, // bus interface input up_rstn, @@ -72,7 +72,7 @@ module axi_dac_interpolate_reg( // internal registers reg [31:0] up_version = {16'h0002, /* MAJOR */ - 8'h04, /* MINOR */ + 8'h05, /* MINOR */ 8'h00}; /* PATCH */ reg [31:0] up_scratch = 32'h0; @@ -84,7 +84,7 @@ module axi_dac_interpolate_reg( reg [ 1:0] up_config = 2'h0; reg [15:0] up_correction_coefficient_a = 16'h0; reg [15:0] up_correction_coefficient_b = 16'h0; - reg [19:0] up_trigger_config = 20'h0; + reg [20:0] up_trigger_config = 21'h0; reg [15:0] up_dac_raw_ch_a_data; reg [15:0] up_dac_raw_ch_b_data; @@ -141,7 +141,7 @@ module axi_dac_interpolate_reg( up_correction_coefficient_b <= up_wdata[15:0]; end if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin - up_trigger_config <= up_wdata[19:0]; + up_trigger_config <= up_wdata[20:0]; end if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin up_dac_raw_ch_a_data <= up_wdata[15:0]; @@ -170,7 +170,7 @@ module axi_dac_interpolate_reg( 5'h15: up_rdata <= {30'h0,up_config}; 5'h16: up_rdata <= {16'h0,up_correction_coefficient_a}; 5'h17: up_rdata <= {16'h0,up_correction_coefficient_b}; - 5'h18: up_rdata <= {12'h0,up_trigger_config}; + 5'h18: up_rdata <= {11'h0,up_trigger_config}; 5'h19: up_rdata <= {up_dac_raw_ch_b_data, up_dac_raw_ch_a_data}; default: up_rdata <= 0; endcase @@ -189,7 +189,7 @@ module axi_dac_interpolate_reg( up_config[0], // 1 up_correction_coefficient_b,// 16 up_correction_coefficient_a,// 16 - up_trigger_config, // 20 + up_trigger_config, // 21 up_flags, // 6 up_dac_raw_ch_a_data, // 16 up_dac_raw_ch_b_data, // 16 @@ -205,7 +205,7 @@ module axi_dac_interpolate_reg( dac_correction_enable_a, // 1 dac_correction_coefficient_b, // 16 dac_correction_coefficient_a, // 16 - trigger_config, // 20 + trigger_config, // 21 flags, // 6 dac_raw_ch_a_data, // 16 dac_raw_ch_b_data, // 16 diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl index 5a5c68e2a7d..e7fef7ee014 100644 --- a/projects/m2k/common/m2k_bd.tcl +++ b/projects/m2k/common/m2k_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -266,6 +266,9 @@ ad_connect axi_dac_interpolate/trigger_la logic_analyzer/trigger_out_adc ad_connect axi_dac_interpolate/dac_valid_out_a axi_ad9963/dma_valid_i ad_connect axi_dac_interpolate/dac_valid_out_b axi_ad9963/dma_valid_q +ad_connect axi_dac_interpolate/last_a ad9963_dac_dmac_a/m_axis_last +ad_connect axi_dac_interpolate/last_b ad9963_dac_dmac_b/m_axis_last + ad_connect /axi_ad9963/tx_data txd ad_connect /axi_ad9963/tx_iq txiq ad_connect /axi_ad9963/tx_clk tx_clk