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mc6800.js
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mc6800.js
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/*
*
* JSMSX - MSX Emulator in Javascript
* Copyright (c) 2006 Marcus Granado <mrc.gran(@)gmail.com>
*
* Portions of the initial code was inspired by the work of
* Arnon Cardoso's Java MSX Emulator and
* Adam Davidson & Andrew Pollard's Z80 class of the Spectrum Java Emulator
* after reading this thread: http://www.msx.org/forumtopic4176.html
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
* The full license is available at http://www.gnu.org/licenses/gpl.html
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Completely revamped to the MC6800 CPU by Dave Roberts based on the work of William Beech.
* January 2018 - Further updated by Jon Stanley with some reorganization and TekExtended instructions.
*
* m6800.c: SWTP 6800 CPU simulator
Copyright (c) 2005-2011, William Beech
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of William A. Beech shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from William A. Beech.
*
*/
function TekCpu(hw) {
// Establish the MIPS = Millions of Instructions Per Second
// 0.833 is specific to the 6800 processor
const MIPS = 0.833;
// When the TekCpu object is created, its execute() function will
// be called 100 times per second in a SetInterval. To faithfully emulate
// the actual speed of a 6800, compute the number of instructions that will
// be executed in one execute() function call interval.
const InstructionsPerInterval = (MIPS*1000000/408); // profiled to match my 4051 benchmarks
//console.log("InstructionsPerInterval = " + InstructionsPerInterval);
// Change this value to true if you want to see some processor executions logged to the console
const DebugExecutePrint = false;
var instruction_mnemonic;
var instruction_operand;
var instruction_description;
var oldNMI = 0;
var oldIRQ = 0;
var lastPC = 0xDEAD;
// NOTE: The Motorola MC6800 stores the most significant byte of a word at the lower address.
// -------------------------------------------------------------------------------------
// 6800 vectors
// -------------------------------------------------------------------------------------
const IRQ_VECTOR = 0xFFF8;
const SWI_VECTOR = 0xFFFA;
const NMI_VECTOR = 0xFFFC;
const RESET_VECTOR = 0xFFFE;
// -------------------------------------------------------------------------------------
// 6800 registers
// -------------------------------------------------------------------------------------
var A = 0x00; // Accumulator A (8 bits)
var B = 0x00; // Accumulator B (8 bits)
var IX = 0x0000; // Index register (16 bits)
var PC = 0x0000; // Program counter (16 bits)
var SP = 0x0000; // Stack pointer (16 bits)
var CCR = 0x00; // Condition code register (8 separate bits) aka Status Register
var IR = 0x00; // Instruction Register (8 bits)
// -------------------------------------------------------------------------------------
// 6800 bit constants
// -------------------------------------------------------------------------------------
const ADDR_MASK = 0xFFFF; // 16 bits.
// Flag bit positions in CCR
const FS = 0x80; // Fetch Space (ROM) select - Tektronix 4052/54 only
const DS = 0x40; // Data Space (RAM) select - Tektronix 4052/54 only
const HF = 0x20; // Half carry
const IF = 0x10; // Interrupt mask
const NF = 0x08; // Negative
const ZF = 0x04; // Zero
const VF = 0x02; // Overflow
const CF = 0x01; // Carry
// For a 6800, the upper 2 bits of the CCR are unused
const CCR_ALWAYS_ON = 0xC0;
const CCR_MASK = HF | IF | NF | ZF | VF | CF;
// -------------------------------------------------------------------------------------
// Condition Code Register (aka Status Register) helper functions
// -------------------------------------------------------------------------------------
function TOGGLE_FLAG( FLAG ) {
CCR ^= FLAG;
}
function GET_FLAG( FLAG ) {
if( CCR & FLAG ) return 1;
else return 0;
}
function SET_FLAG( FLAG ) {
CCR |= FLAG;
}
function CLR_FLAG( FLAG ) {
CCR &= ~FLAG;
}
function GET_FLAG_BITS( FLAG ) {
return CCR & FLAG;
}
function COND_SET_FLAG( COND, FLAG ) {
if( COND ) SET_FLAG( FLAG );
else CLR_FLAG( FLAG );
}
function COND_SET_FLAG_N( VAR ) {
if( VAR & 0x80 ) SET_FLAG( NF );
else CLR_FLAG( NF );
}
function COND_SET_FLAG_Z( VAR ) {
if( VAR == 0 ) SET_FLAG( ZF );
else CLR_FLAG( ZF );
}
function COND_SET_FLAG_H( COND ) {
if( COND ) SET_FLAG( HF );
else CLR_FLAG( HF );
}
function COND_SET_FLAG_C( VAR ) {
if( VAR & 0x100 ) SET_FLAG( CF );
else CLR_FLAG( CF );
}
function COND_SET_FLAG_V( COND ) {
if( COND ) SET_FLAG( VF );
else CLR_FLAG( VF );
}
// -------------------------------------------------------------------------------------
// Memory access functions
// -------------------------------------------------------------------------------------
function readByte( address ) {
// This calls the hardware outside of the CPU object
return hw.peekb( address );
}
function writeByte( address, val ) {
// This calls the hardware outside of the CPU object
return hw.pokeb( address, val );
}
function readWord( address ) {
var temp = address;
var val = readByte( temp ) << 8; // MSB
val |= readByte( ++temp & ADDR_MASK ) ; // LSB
return val;
}
function writeWord( address, val ) {
writeByte( (address+0) & ADDR_MASK, (val >>> 8) & 0xFF ); // MSB
writeByte( (address+1) & ADDR_MASK, (val >>> 0) & 0xFF ); // LSB
}
// -------------------------------------------------------------------------------------
// Memory access helper functions for instruction and operand read and write accesses
// -------------------------------------------------------------------------------------
// fetch a byte from location in PC
function fetch_byte() {
var val = readByte( PC ) & 0xFF; // fetch byte at address in PC
PC = (PC + 1) & ADDR_MASK; // increment PC by 1
return val;
}
// fetch a 16-bit word from location in PC
function fetch_word() {
var val = readByte( PC ) << 8; // fetch high byte
val |= readByte( PC + 1 ) & 0xFF; // fetch low byte
PC = (PC + 2) & ADDR_MASK; // increment PC by 2
return val;
}
// push a byte to the stack and decrement Stack Pointer
function push_byte( val ) {
writeByte( SP, val & 0xFF ); // push byte at address in SP
SP = (SP - 1) & ADDR_MASK; // decrement SP by 1
}
// push a 16-bit word to the stack (2 byte pushes)
function push_word( val ) {
push_byte( val & 0xFF ); // push low byte
push_byte( val >>> 8 ); // push high byte
}
// pop a byte from the stack and increment Stack Pointer
function pop_byte() {
SP = (SP + 1) & ADDR_MASK; // increment SP by 1
return readByte( SP ); // fetch byte at address in SP
}
// pop a 16-bit word from the stack (2 byte pops)
function pop_word() {
var res = pop_byte() << 8; // fetch high byte
res |= pop_byte(); // fetch low byte
return res;
}
// -------------------------------------------------------------------------------------
// Helper function for branch instruction execution and decision making
// -------------------------------------------------------------------------------------
// PC will jump to relative offset if the condition is met, otherwise PC remains unchanged
function branch_relative( cond ) {
// Fetch relative offset from memory
var temp = get_relative_addr();
if( cond ) {
PC += temp;
// console.log('>>> BRANCH TAKEN <<<');
} else {
// console.log('>>> BRANCH NOT TAKEN <<<');
}
// Keep address truncated to 16-bits
PC &= ADDR_MASK;
}
// -------------------------------------------------------------------------------------
// Address operand fetch and computation helper functions for instruction execution
// -------------------------------------------------------------------------------------
// Summary of Address Modes:
// 1. Relative - 8-bit sign extended address from 2nd operand is added to PC
// 2. Direct - 8-bit absolute address from 2nd operand for lower 256 bytes of memory
// 3. Extended - 16-bit absolute address from 2nd operand = upper, 3rd operand = lower
// 4. Indexed - 8-bit zero-extended address from 2nd operand is added to 16-bit Index Register (IX)
// returns the relative offset (8-bits) sign-extended at the address pointed to by PC
// rel_addr = sign_extend(operand byte)
function get_relative_addr() {
instruction_operand = ", RELATIVE";
var temp = fetch_byte(); // fetch byte at location in PC
if( temp & 0x80 ) // Sign-extend offset if MSB is set
temp |= 0xFF00;
return temp & ADDR_MASK;
}
// returns the data value at the direct address pointed to by PC
function get_direct_data() {
return readByte( get_direct_addr() );
}
// returns the direct address (8-bits) pointed to by PC
// dir_addr = operand byte
function get_direct_addr() {
instruction_operand = ", DIRECT";
return fetch_byte() & 0xFF; // fetch byte at location in PC
}
// returns the data value at the indexed (indirect) address
function get_indexed_data() {
return readByte( get_indexed_addr() );
}
// returns the indexed (indirect) address pointed to by PC relative to Index Register
// indir_addr = operand byte + IX
function get_indexed_addr() {
instruction_operand = ", INDIRECT";
return (fetch_byte() + IX) & ADDR_MASK; // fetch byte at location in PC and offset by IX
}
// returns the data value at the extended address pointed to by PC
function get_extended_data() {
return readByte( get_extended_addr() );
}
// returns the extended (16-bit) direct address pointed to by PC
// ext_addr = 16-bit operand word
function get_extended_addr() {
instruction_operand = ", EXTENDED";
return fetch_word(); // fetch 16-bit word at location in PC
}
// -------------------------------------------------------------------------------------
// This is THE processor instruction execution function
// -------------------------------------------------------------------------------------
this.execute = function() {
var DAR, hi, lo, op1, res;
// Execute only InstructionsPerInterval amount of instructions to emulate the CPU speed
for(i = 0; i < InstructionsPerInterval; i++) {
lastPC = PC;
// -------------------------------------------------------------------------------------
// Output some status based on useful PC addresses
// -------------------------------------------------------------------------------------
// if( lastPC == 0xCBBF ) hw.println( 'DER: MC6800.js >>>>> CRTRST: <<<<<' );
// if( lastPC == 0xC888 ) hw.println( 'DER: MC6800.js >>>>> CHSCAN: <<<<<' );
// if( lastPC == 0xCBEE ) hw.println( 'DER: MC6800.js >>>>> PCHAR: <<<<<' );
// if( lastPC == 0xC5B2 ) hw.println( 'DER: MC6800.js >>>>> IDLE: <<<<<' );
// if( lastPC == 0xC65C ) hw.println( 'DER: MC6800.js >>>>> CIDLE: <<<<<' );
// -------------------------------------------------------------------------------------
// Process interrupts
// -------------------------------------------------------------------------------------
if( hw.checkNMI() ) {
if( !oldNMI ) {
push_word( PC );
push_word( IX );
push_byte( A );
push_byte( B );
push_byte( CCR );
SET_FLAG( IF );
PC = readWord(NMI_VECTOR) & ADDR_MASK;
lastPC = PC;
//console.log(' >>>>> NMI <<<<<' );
}
oldNMI = 1;
} else {
oldNMI = 0;
if( hw.checkIRQ() ) {
if( !GET_FLAG_BITS( IF ) ) {
if( !oldIRQ ) {
push_word( PC );
push_word( IX );
push_byte( A );
push_byte( B );
push_byte( CCR );
SET_FLAG( IF );
PC = readWord(IRQ_VECTOR) & ADDR_MASK;
lastPC = PC;
//console.log(' >>>>> IRQ <<<<<' );
}
oldIRQ = 1;
} else {
oldIRQ = 0;
}
} else {
oldIRQ = 0;
}
}
// -------------------------------------------------------------------------------------
// Fetch instruction at Program Counter (PC) address, decode and execute the instruction
// -------------------------------------------------------------------------------------
IR = fetch_byte();
switch( IR ) {
case 0x01:
instruction_mnemonic = "NOP";
instruction_description = "(6800) No operation";
break;
case 0x02:
instruction_mnemonic = "NOP2";
instruction_description = "(TekExtended) No operation";
break;
case 0x03:
instruction_mnemonic = "SFA";
instruction_description = "(TekExtended) Store A <= F?";
i = 0;
break;
case 0x05:
instruction_mnemonic = "TAP";
instruction_description = "(TekExtended) Transfer Status Register P <= A?";
// This might be a specific TAP for ROM/RAM space control to CCR bits 6-7?";
i = 0;
break;
case 0x06:
instruction_mnemonic = "TAP";
instruction_description = "(6800) Transfer Status Register P <= A";
CCR = A & this.CCR_MASK;
break;
case 0x07:
instruction_mnemonic = "TPA";
instruction_description = "(6800) Transfer A <= Status Register P";
A = CCR | CCR_ALWAYS_ON;
break;
case 0x08:
instruction_mnemonic = "INX";
instruction_description = "(6800) Increment IX";
IX = (IX + 1) & ADDR_MASK;
COND_SET_FLAG_Z( IX );
break;
case 0x09:
instruction_mnemonic = "DEX";
instruction_description = "(6800) Decrement IX";
IX = (IX - 1) & ADDR_MASK;
COND_SET_FLAG_Z( IX );
break;
case 0x0A:
instruction_mnemonic = "CLV";
instruction_description = "(6800) Clear overflow status bit";
CLR_FLAG( VF );
break;
case 0x0B:
instruction_mnemonic = "SEV";
instruction_description = "(6800) Set overflow status bit";
SET_FLAG( VF );
break;
case 0x0C:
instruction_mnemonic = "CLC";
instruction_description = "(6800) Clear carry status bit";
CLR_FLAG( CF );
break;
case 0x0D:
instruction_mnemonic = "SEC";
instruction_description = "(6800) Set carry status bit";
SET_FLAG( CF );
break;
case 0x0E:
instruction_mnemonic = "CLI";
instruction_description = "(6800) Clear interrupt mask status bit";
CLR_FLAG( IF );
break;
case 0x0F:
instruction_mnemonic = "SEI";
instruction_description = "(6800) Set interrupt mask status bit";
SET_FLAG( IF );
break;
case 0x10:
instruction_mnemonic = "SBA";
instruction_description = "(6800) Store A <= A - B";
op1 = B;
res = A - op1;
COND_SET_FLAG_V( (A ^ op1 ^ res ^ (res >>> 1)) & 0x80 );
COND_SET_FLAG_C( res );
A = res & 0xFF;
COND_SET_FLAG_Z( A );
COND_SET_FLAG_N( A );
break;
case 0x11:
instruction_mnemonic = "CBA";
instruction_description = "(6800) Compare A - B";
op1 = B;
res = A - op1;
COND_SET_FLAG_V( (A ^ op1 ^ res ^ (res >>> 1)) & 0x80 );
COND_SET_FLAG_C( res );
COND_SET_FLAG_Z( res & 0xFF );
COND_SET_FLAG_N( res & 0xFF );
break;
case 0x12:
instruction_mnemonic = "TAPX";
instruction_description = "(TekExtended) Transfer Extended Status Register PX <= A?";
i = 0;
break;
case 0x13:
instruction_mnemonic = "TPAX";
instruction_description = "(TekExtended) Transfer A <= Extended Status Register?";
i = 0;
break;
case 0x14:
instruction_mnemonic = "ADXI";
instruction_description = "(TekExtended) ???";
i = 0;
break;
case 0x15:
instruction_mnemonic = "ASPI";
instruction_description = "(TekExtended) ???";
i = 0;
break;
case 0x16:
instruction_mnemonic = "TAB";
instruction_description = "(6800) Transfer A => B";
B = A;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
CLR_FLAG( VF );
break;
case 0x17:
instruction_mnemonic = "TBA";
instruction_description = "(6800) Transfer B => A";
A = B;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
CLR_FLAG( VF );
break;
case 0x18:
instruction_mnemonic = "SDA";
instruction_description = "(TekExtended) Store A <= D?";
i = 0;
break;
case 0x19:
instruction_mnemonic = "DAA";
instruction_description = "(6800) Decimal Adjust Accumulator A";
// Note: TekExtended version does NOT implement this instruction
DAR = A & 0x0F;
op1 = GET_FLAG( CF );
if( (DAR > 9) || GET_FLAG( CF ) ) {
DAR += 6;
A &= 0xF0;
A |= (DAR & 0x0F);
COND_SET_FLAG( DAR & 0x10, CF );
}
DAR = (A >>> 4) & 0x0F;
if( (DAR > 9) || GET_FLAG( CF ) ) {
DAR += 6;
if( GET_FLAG( CF ) )
DAR++;
A &= 0x0F;
A |= (DAR << 4);
}
COND_SET_FLAG( op1, CF );
if( (DAR << 4) & 0x100 )
SET_FLAG( CF );
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
A &= 0xFF;
break;
case 0x1A:
instruction_mnemonic = "NLDXX";
instruction_description = "(TekExtended) N Load IX <= M(indexed)?";
i = 0;
break;
case 0x1B:
instruction_mnemonic = "ABA";
instruction_description = "(6800) A <= A + B";
op1 = B;
res = A + op1;
COND_SET_FLAG_H( (A ^ op1 ^ res) & 0x10 );
COND_SET_FLAG_V( (A ^ op1 ^ res ^ (res >>> 1)) & 0x80 );
COND_SET_FLAG_C( res );
A = res & 0xFF;
COND_SET_FLAG_Z( A );
COND_SET_FLAG_N( A );
break;
case 0x1C:
instruction_mnemonic = "NLDAX";
instruction_description = "(TekExtended) N Load IX <= A?";
i = 0;
break;
case 0x1D:
instruction_mnemonic = "NLDBX";
instruction_description = "(TekExtended) N Load IX <= B?";
i = 0;
break;
case 0x1E:
instruction_mnemonic = "NSTAX";
instruction_description = "(TekExtended) N Store A <= IX?";
i = 0;
break;
case 0x1F:
instruction_mnemonic = "JMPAX";
instruction_description = "(TekExtended) Jump A IX?";
i = 0;
break;
case 0x20:
instruction_mnemonic = "BRA";
instruction_description = "(6800) Branch Always";
branch_relative( 1 );
break;
case 0x21:
instruction_mnemonic = "SDB";
instruction_description = "(TekExtended) Store or subtract B <= D? Direct?";
i = 0;
break;
case 0x22:
instruction_mnemonic = "BHI";
instruction_description = "(6800) Branch if Higher (unsigned)";
branch_relative( !(GET_FLAG(CF) | GET_FLAG(ZF)) );
break;
case 0x23:
instruction_mnemonic = "BLS";
instruction_description = "(6800) Branch if Lower or Same (unsigned)";
branch_relative( GET_FLAG(CF) | GET_FLAG(ZF) );
break;
case 0x24:
instruction_mnemonic = "BCC";
instruction_description = "(6800) Branch if Carry Clear (CF = 0)";
branch_relative( !GET_FLAG(CF) );
break;
case 0x25:
instruction_mnemonic = "BCS";
instruction_description = "(6800) Branch if Carry Set (CF = 1)";
branch_relative( GET_FLAG(CF) );
break;
case 0x26:
instruction_mnemonic = "BNE";
instruction_description = "(6800) Branch if Not Equal (ZF = 0)";
branch_relative( !GET_FLAG(ZF) );
break;
case 0x27:
instruction_mnemonic = "BEQ";
instruction_description = "(6800) Branch if Equal (ZF = 1)";
branch_relative( GET_FLAG(ZF) );
break;
case 0x28:
instruction_mnemonic = "BVC";
instruction_description = "(6800) Branch if Overflow Clear (VF = 0)";
branch_relative( !GET_FLAG(VF) );
break;
case 0x29:
instruction_mnemonic = "BVS";
instruction_description = "(6800) Branch if Overflow Set (VF = 1)";
branch_relative( GET_FLAG(VF) );
break;
case 0x2A:
instruction_mnemonic = "BPL";
instruction_description = "(6800) Branch if Plus/Positive (N = 0)";
branch_relative( !GET_FLAG(NF) );
break;
case 0x2B:
instruction_mnemonic = "BMI";
instruction_description = "(6800) Branch if Minus/Negative (N = 1)";
branch_relative( GET_FLAG(NF) );
break;
case 0x2C:
instruction_mnemonic = "BGE";
instruction_description = "(6800) Branch if Greater or Equal (signed)";
branch_relative( !(GET_FLAG(NF) ^ GET_FLAG(VF)) );
break;
case 0x2D:
instruction_mnemonic = "BLT";
instruction_description = "(6800) Branch if Less Than (signed)";
branch_relative( GET_FLAG(NF) ^ GET_FLAG(VF) );
break;
case 0x2E:
instruction_mnemonic = "BGT";
instruction_description = "(6800) Branch if Greater Than (signed)";
branch_relative( !(GET_FLAG(ZF) | (GET_FLAG(NF) ^ GET_FLAG(VF))) );
break;
case 0x2F:
instruction_mnemonic = "BLE";
instruction_description = "(6800) Branch if Less or Equal (signed)";
branch_relative( GET_FLAG(ZF) | (GET_FLAG(NF) ^ GET_FLAG(VF)) );
break;
case 0x30:
instruction_mnemonic = "TSX";
instruction_description = "(6800) Transfer IX <= SP + 1";
IX = (SP + 1) & ADDR_MASK;
break;
case 0x31:
instruction_mnemonic = "INS";
instruction_description = "(6800) Increment SP";
SP = (SP + 1) & ADDR_MASK;
break;
case 0x32:
instruction_description = "(6800) Pull/Pop Stack to A";
instruction_mnemonic = "PUL A";
A = pop_byte();
break;
case 0x33:
instruction_mnemonic = "PUL B";
instruction_description = "(6800) Pull/Pop Stack to B";
B = pop_byte();
break;
case 0x34:
instruction_mnemonic = "DES";
instruction_description = "(6800) Decrement SP";
SP = (SP - 1) & ADDR_MASK;
break;
case 0x35:
instruction_mnemonic = "TXS";
instruction_description = "(6800) Transfer SP <= IX - 1";
SP = (IX - 1) & ADDR_MASK;
break;
case 0x36:
instruction_mnemonic = "PSH A";
instruction_description = "(6800) Push A to Stack";
push_byte( A );
break;
case 0x37:
instruction_mnemonic = "PSH B";
instruction_description = "(6800) Push B to Stack";
push_byte( B );
break;
case 0x38:
instruction_mnemonic = "JMPIN";
instruction_description = "(TekExtended) Jump IN? Extended";
i = 0;
break;
case 0x39:
instruction_mnemonic = "RTS";
instruction_description = "(6800) Return from Subroutine - Pop Stack to PC";
PC = pop_word();
break;
case 0x3A:
instruction_mnemonic = "FPSHD";
instruction_description = "(TekExtended) Function Push M(direct)";
i = 0;
break;
case 0x3B:
instruction_mnemonic = "RTI";
instruction_description = "(6800) Return from Interrupt - Pop Stack and restore Registers";
CCR = pop_byte();
B = pop_byte();
A = pop_byte();
IX = pop_word();
PC = pop_word();
break;
case 0x3C:
instruction_mnemonic = "FPSHX";
instruction_description = "(TekExtended) Function Push M(indexed)";
i = 0;
break;
case 0x3D:
instruction_mnemonic = "FPSH";
instruction_description = "(TekExtended) Function Push M(extended)";
i = 0;
break;
case 0x3E:
instruction_mnemonic = "WAI";
instruction_description = "(6800) Wait For Interrupt - Push Registers to Stack and jump to Reset vector";
push_word( PC );
push_word( IX );
push_byte( A );
push_byte( B );
push_byte( CCR );
if( GET_FLAG(IF) ) {
//@@@ reason = STOP_HALT;
//@@@ continue;
} else {
SET_FLAG( IF );
// Fetch the Reset vector for the PC to jump to the WAI routine
// This halts the processor until a non-maskable interrupt arrives
PC = readWord(RESET_VECTOR) & ADDR_MASK;
}
break;
case 0x3F:
instruction_mnemonic = "SWI";
instruction_description = "(6800) Software Interrupt - Push Registers to Stack and jump to SWI vector";
push_word( PC );
push_word( IX );
push_byte( A );
push_byte( B );
push_byte( CCR );
SET_FLAG( IF );
// Fetch the SWI interrupt vector for the PC to jump to the SWI routine
PC = readWord(SWI_VECTOR) & ADDR_MASK;
break;
case 0x40:
instruction_mnemonic = "NEG A";
instruction_description = "(6800) Negate A";
A = (0 - A) & 0xFF;
COND_SET_FLAG_V( A == 0x80 );
COND_SET_FLAG( A == 0x00, CF );
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
break;
case 0x41:
instruction_mnemonic = "FPSHI";
instruction_description = "(TekExtended) Function Push Immediate";
i = 0;
break;
case 0x3D:
instruction_mnemonic = "FPULD";
instruction_description = "(TekExtended) Function Pull/Pop from M(direct)?";
i = 0;
break;
case 0x43:
instruction_mnemonic = "COM A";
instruction_description = "(6800) Ones Complement A";
A = (~A) & 0xFF;
CLR_FLAG( VF );
SET_FLAG( CF );
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
break;
case 0x44:
instruction_mnemonic = "LSR A";
instruction_description = "(6800) Logical Shift Right A";
COND_SET_FLAG( A & 0x01, CF );
A = (A >>> 1) & 0xFF;
CLR_FLAG( NF );
COND_SET_FLAG_Z( A );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x45:
instruction_mnemonic = "FPULX";
instruction_description = "(TekExtended) Function Pull/Pop from M(indexed)?";
i = 0;
break;
case 0x46:
instruction_mnemonic = "ROR A";
instruction_description = "(6800) Rotate Right A";
hi = GET_FLAG( CF );
COND_SET_FLAG( A & 0x01, CF );
A = (A >>> 1) & 0xFF;
if( hi )
A |= 0x80;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x47:
instruction_mnemonic = "ASR A";
instruction_description = "(6800) Arithmetic Shift Right A";
COND_SET_FLAG( A & 0x01, CF );
lo = A & 0x80;
A = (A >>> 1) & 0xFF;
A |= lo;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x48:
instruction_mnemonic = "ASL A";
instruction_description = "(6800) Arithmetic Shift Left A";
COND_SET_FLAG( A & 0x80, CF );
A = (A << 1) & 0xFF;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x49:
instruction_mnemonic = "ROL A";
instruction_description = "(6800) Rotate Left A";
hi = GET_FLAG( CF );
COND_SET_FLAG( A & 0x80, CF );
A = (A << 1) & 0xFF;
if( hi )
A |= 0x01;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x4A:
instruction_mnemonic = "DEC A";
instruction_description = "(6800) Decrement A";
COND_SET_FLAG_V( A == 0x80 );
A = (A - 1) & 0xFF;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
break;
case 0x4B:
instruction_mnemonic = "FPUL";
instruction_description = "(TekExtended) Function Pull/Pop from M(extended)";
i = 0;
break;
case 0x4C:
instruction_mnemonic = "INC A";
instruction_description = "(6800) Increment A";
COND_SET_FLAG_V( A == 0x7F );
A = (A + 1) & 0xFF;
COND_SET_FLAG_N( A );
COND_SET_FLAG_Z( A );
break;
case 0x4D:
instruction_mnemonic = "TST A";
instruction_description = "(6800) Test A";
lo = (A - 0) & 0xFF;
CLR_FLAG( VF );
CLR_FLAG( CF );
COND_SET_FLAG_N( lo );
COND_SET_FLAG_Z( lo );
break;
case 0x4E:
instruction_mnemonic = "FDUP";
instruction_description = "(TekExtended) Function DUP? Duplicate?";
i = 0;
break;
case 0x4F:
instruction_mnemonic = "CLR A";
instruction_description = "(6800) Clear A";
A = 0;
CLR_FLAG( NF );
CLR_FLAG( VF );
CLR_FLAG( CF );
SET_FLAG( ZF );
break;
case 0x50:
instruction_mnemonic = "NEG B";
instruction_description = "(6800) Negate B";
B = (0 - B) & 0xFF;
COND_SET_FLAG_V( B == 0x80 );
COND_SET_FLAG( B == 0x00, CF );
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
break;
case 0x51:
instruction_mnemonic = "FSWP";
instruction_description = "(TekExtended) Function SWP?";
i = 0;
break;
case 0x52:
instruction_mnemonic = "FADD";
instruction_description = "(TekExtended) Function Add";
i = 0;
break;
case 0x53:
instruction_mnemonic = "COM B";
instruction_description = "(6800) Ones Complement B";
B = (~B) & 0xFF;
CLR_FLAG( VF );
SET_FLAG( CF );
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
break;
case 0x54:
instruction_mnemonic = "LSR B";
instruction_description = "(6800) Logical Shift Right B";
COND_SET_FLAG( B & 0x01, CF );
B = (B >>> 1) & 0xFF;
CLR_FLAG( NF );
COND_SET_FLAG_Z( B );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x55:
instruction_mnemonic = "FSUB";
instruction_description = "(TekExtended) Function Subtract";
i = 0;
break;
case 0x56:
instruction_mnemonic = "ROR B";
instruction_description = "(6800) Rotate Right B";
hi = GET_FLAG( CF );
COND_SET_FLAG( B & 0x01, CF );
B = (B >>> 1) & 0xFF;
if( hi )
B |= 0x80;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x57:
instruction_mnemonic = "ASR B";
instruction_description = "(6800) Arithmetic Shift Right B";
COND_SET_FLAG( B & 0x01, CF );
lo = B & 0x80;
B = (B >>> 1) & 0xFF;
B |= lo;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF));
break;
case 0x58:
instruction_mnemonic = "ASL B";
instruction_description = "(6800) Arithmetic Shift Left B";
COND_SET_FLAG( B & 0x80, CF );
B = (B << 1) & 0xFF;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x59:
instruction_mnemonic = "ROL B";
instruction_description = "(6800) Rotate Left B";
hi = GET_FLAG( CF );
COND_SET_FLAG( B & 0x80, CF );
B = (B << 1) & 0xFF;
if( hi )
B |= 0x01;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
COND_SET_FLAG_V( GET_FLAG(NF) ^ GET_FLAG(CF) );
break;
case 0x5A:
instruction_mnemonic = "DEC B";
instruction_description = "(6800) Decrement B";
COND_SET_FLAG_V( B == 0x80 );
B = (B - 1) & 0xFF;
COND_SET_FLAG_N( B );
COND_SET_FLAG_Z( B );
break;
case 0x5B:
instruction_mnemonic = "FMUL";
instruction_description = "(TekExtended) Function Multiply";
i = 0;
break;
case 0x5C: