Intermediate #3
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Intermediate #3
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commit e5d99b8bf3ec691057a7aaeb87cd6144c14dc55b Author: David Lutze <[email protected]> Date: Wed Jan 17 16:40:21 2024 +0100 added vc tests commit 15485449becf7381e01c26fdcae401bde04f24c2 Author: David Lutze <[email protected]> Date: Wed Jan 17 16:39:25 2024 +0100 added some tests
…me/tchecker into develop/implementing-bisim
commit e5d99b8bf3ec691057a7aaeb87cd6144c14dc55b Author: David Lutze <[email protected]> Date: Wed Jan 17 16:40:21 2024 +0100 added vc tests commit 15485449becf7381e01c26fdcae401bde04f24c2 Author: David Lutze <[email protected]> Date: Wed Jan 17 16:39:25 2024 +0100 added some tests
…me/tchecker into HEAD
added more system tests added test wip wip wip rename added oracle for 64bit first version wip wip
alzeha
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Sep 24, 2024
* fixing pipeline, linux only * added first version of vcg * Intermediate (#3) very first working version * aligning code to the TR * Wip (#4) * wip * aligning to TR * improved readability and counting each alternating seq only once * updated doc * wip * enabled the possibility to do the extrapolation by hand * some renaming * wip * added urgent and committed loc * added automaton for non deterministic evaluation * fix * changed tchecker::clock_id_t to int * deleted non existing files of master * fixed changed function names of get_no_of_virtual_clocks in test-virtual_constraint.hh * removed part of the code which was not present anymore in master * cleanup --------- Co-authored-by: Schulzen <[email protected]>
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