HDL files for 2-24 GHz XMW TX/RX Platforms

Adding required config/source files for XMW TX and RX projects on ZCU102

Signed-off-by: Reema Saleem <[email protected]>

projects/ad9082_fmca_ebz_xmw_rx/Makefile

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+####################################################################################
+## Copyright (c) 2018 - 2021 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk

projects/ad9082_fmca_ebz_xmw_rx/Readme.md

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+# AD9082-FMCA-EBZ-XMW-RX HDL Project
+
+Here are some pointers to help you:
+  * Parts : [MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC](https://www.analog.com/ad9082)
+  * Project Doc: https://wiki.analog.com/resources/eval/developer-kits/2to24ghz-mxfe-rf-front-end
+  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl
+  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081

projects/ad9082_fmca_ebz_xmw_rx/zcu102/Makefile

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+####################################################################################
+## Copyright (c) 2018 - 2021 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad9082_fmca_ebz_xmw_rx_zcu102
+
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
+M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
+M_DEPS += ../../ad9081_fmca_ebz/zcu102/timing_constr.xdc
+M_DEPS += ../../ad9082_fmca_ebz_xmw_rx/zcu102/system_top.v
+M_DEPS += ../../ad9082_fmca_ebz_xmw_rx/zcu102/system_constr.xdc
+M_DEPS += ../../ad9081_fmca_ebz/zcu102/system_bd.tcl
+M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
+M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
+M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_3w_spi.v
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_sysid
+LIB_DEPS += axi_tdd
+LIB_DEPS += data_offload
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
+LIB_DEPS += jesd204/axi_jesd204_rx
+LIB_DEPS += jesd204/axi_jesd204_tx
+LIB_DEPS += jesd204/jesd204_rx
+LIB_DEPS += jesd204/jesd204_tx
+LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx
+LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_adcfifo
+LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
+LIB_DEPS += util_pack/util_cpack2
+LIB_DEPS += util_pack/util_upack2
+LIB_DEPS += util_tdd_sync
+LIB_DEPS += xilinx/axi_adxcvr
+LIB_DEPS += xilinx/util_adxcvr
+
+include ../../scripts/project-xilinx.mk

projects/ad9082_fmca_ebz_xmw_rx/zcu102/system_bd.tcl

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+
+source $ad_hdl_dir/projects/ad9081_fmca_ebz/zcu102/system_bd.tcl
+

projects/ad9082_fmca_ebz_xmw_rx/zcu102/system_project.tcl

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+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
+#      make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
+
+#
+# Parameter description:
+#   JESD_MODE : Used link layer encoder mode
+#      64B66B - 64b66b link layer defined in JESD 204C
+#      8B10B  - 8b10b link layer defined in JESD 204B
+#
+#   RX_RATE :  Line rate of the Rx link ( MxFE to FPGA )
+#   TX_RATE :  Line rate of the Tx link ( FPGA to MxFE )
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
+#   [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
+#
+#
+#  !!! For this carrier only 8B10B mode is supported !!!
+#
+
+adi_project ad9082_fmca_ebz_xmw_rx_zcu102 0 [list \
+  JESD_MODE    [get_env_param JESD_MODE    8B10B ]\
+  RX_LANE_RATE [get_env_param RX_RATE      15 ] \
+  TX_LANE_RATE [get_env_param TX_RATE      15 ] \
+  RX_JESD_M    [get_env_param RX_JESD_M    4 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    8 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  RX_JESD_NP   [get_env_param RX_JESD_NP   16] \
+  RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    4 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    8 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+  TX_JESD_NP   [get_env_param TX_JESD_NP   16] \
+  TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
+]
+
+adi_project_files ad9082_fmca_ebz_xmw_rx_zcu102 [list \
+  "../../ad9082_fmca_ebz_xmw_rx/zcu102/system_top.v" \
+  "../../ad9082_fmca_ebz_xmw_rx/zcu102/system_constr.xdc" \
+  "../../ad9081_fmca_ebz/zcu102/timing_constr.xdc" \
+  "../../../library/common/ad_3w_spi.v" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
+
+
+adi_project_run ad9082_fmca_ebz_xmw_rx_zcu102
+