review changes

- whitespace fixes - reorder spi_engine_create params (using sdo streaming is expected more frequent than other params) - headers on offload files - fix extra pwm params - remove unneeded project files for cora - fix cora critical warning due to wrong axi clkgen instance name - reorganize cora top gpios - wire name fixes on de10nano top Signed-off-by: Laez Barbosa <[email protected]>
analogdevicesinc · Sep 27, 2024 · d9412c4 · d9412c4
1 parent c441d96
commit d9412c4
Show file tree

Hide file tree

Showing 17 changed files with 65 additions and 79 deletions.
diff --git a/docs/library/spi_engine/spi_engine_offload.rst b/docs/library/spi_engine/spi_engine_offload.rst
@@ -48,7 +48,7 @@ Configuration Parameters
    * - NUM_OF_SDI
      - Number of multiple SDI lines, (min: 1, max: 8)
    * - SDO_STREAMING
-     - Enables the s_axis_sdo interface. This allows for sourcing the SDO data 
+     - Enables the s_axis_sdo interface. This allows for sourcing the SDO data
        stream from a DMA or other similar sources, useful for DACs.
 
 Signal and Interface Pins

diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst
@@ -7,19 +7,18 @@ Overview
 --------------------------------------------------------------------------------
 
 This page documents the HDL reference design for the
-:adi:`EVAL-AD5780ARDZ<EVAL-AD5780ARDZ>`, 
-:adi:`EVAL-AD5781ARDZ<EVAL-AD5781ARDZ>` and 
-:adi:`EVAL-AD5791ARDZ <EVAL-AD5791ARDZ>` evaluation boards.
+:adi:`EVAL-AD5780ARDZ`, :adi:`EVAL-AD5781ARDZ` and :adi:`EVAL-AD5791ARDZ`
+evaluation boards.
 
-The :adi:`EVAL-AD5780ARDZ<EVAL-AD5780ARDZ>` facilitates fast prototyping of the
+The :adi:`EVAL-AD5780ARDZ` facilitates fast prototyping of the
 :adi:`AD5780` circuit, and can be substituted with either the :adi:`AD5760` or
-:adi:`AD5790`, which must be ordered separately. Similarly, the 
-:adi:`EVAL-AD5781ARDZ<EVAL-AD5781ARDZ>` and :adi:`EVAL-AD5791ARDZ<EVAL-AD5791ARDZ>` 
+:adi:`AD5790`, which must be ordered separately. Similarly, the
+:adi:`EVAL-AD5781ARDZ` and :adi:`EVAL-AD5791ARDZ`
 come with the :adi:`AD5781` and :adi:`AD5791` respectively.
 
 The :adi:`AD5790`, :adi:`AD5791`, :adi:`AD5760`, :adi:`AD5780` and :adi:`AD5781`
 are a family of precision, single-channel voltage output DACs, with resolutions
-from 16-bits up to 20-bits. They offer guaranteed monotnic operation, and low
+from 16-bits up to 20-bits. They offer guaranteed monotonic operation, and low
 nonlinearity (down to 0.5 LSB INL and DNL)
 
 The evaluation boards provide an on-board -14 V and +14 V dual power supply.
@@ -34,9 +33,9 @@ maximum sample rate.
 Supported boards
 -------------------------------------------------------------------------------
 
--  :adi:`EVAL-AD5780ARDZ <EVAL-AD5780ARDZ>`
--  :adi:`EVAL-AD5781ARDZ <EVAL-AD5781ARDZ>`
--  :adi:`EVAL-AD5791ARDZ <EVAL-AD5791ARDZ>`
+-  :adi:`EVAL-AD5780ARDZ`
+-  :adi:`EVAL-AD5781ARDZ`
+-  :adi:`EVAL-AD5791ARDZ`
 
 Supported devices
 -------------------------------------------------------------------------------
@@ -50,26 +49,28 @@ Supported devices
 Supported carriers
 -------------------------------------------------------------------------------
 
--  :xilinx:`Cora Z7-07S <products/boards-and-kits/1-1qlaz7n.html>` Arduino shield connector
--  :intel:`DE10-Nano <content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>` Arduino shield connector
+-  :xilinx:`Cora Z7-07S <products/boards-and-kits/1-1qlaz7n.html>`
+   Arduino shield connector
+-  :intel:`DE10-Nano <content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>`
+   Arduino shield connector
 
 Block design
 -------------------------------------------------------------------------------
 
-Block diagram
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
 The data path and clock domains are depicted in the below diagrams:
 
-.. image:: ad57xx_de10nano_hdl.svg
+
+.. figure:: ad57xx_de10nano_hdl.svg
    :width: 800
    :align: center
-   :alt: AD5780-ARDZ HDL design block diagram for the DE10-Nano
 
-.. image:: ad57xx_coraz7s_hdl.svg
+   AD5780-ARDZ HDL design block diagram for the DE10-Nano
+
+.. figure:: ad57xx_coraz7s_hdl.svg
    :width: 800
    :align: center
-   :alt: AD5780-ARDZ HDL design block diagram for the Cora Z7-07S
+
+   AD5780-ARDZ HDL design block diagram for the Cora Z7-07S
 
 CPU/Memory interconnects addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl
@@ -3,7 +3,7 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4} {sdo_streaming 1}} {
+proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
   puts "echo_sclk: $echo_sclk"
 
   create_bd_cell -type hier $name

diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -113,8 +113,10 @@ module spi_engine_offload #(
   wire trigger_posedge;
 
   assign cmd_valid = spi_active;
-  assign sdo_data_valid = (sdo_source_select == SDO_SOURCE_STREAM) ? s_axis_sdo_valid : spi_active;
-  assign s_axis_sdo_ready = (sdo_source_select == SDO_SOURCE_STREAM) ? sdo_data_ready : 1'b0;
+  assign sdo_data_valid = (sdo_source_select == SDO_SOURCE_STREAM) ?
+                           s_axis_sdo_valid : spi_active;
+  assign s_axis_sdo_ready = (sdo_source_select == SDO_SOURCE_STREAM) ?
+                             sdo_data_ready : 1'b0;
   assign offload_sdi_valid = sdi_data_valid;
 
   // we don't want to block the SDI interface after disabling the module
@@ -124,7 +126,8 @@ module spi_engine_offload #(
   assign offload_sdi_data = sdi_data;
 
   assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
-  assign sdo_data = (sdo_source_select == SDO_SOURCE_STREAM) ? s_axis_sdo_data : sdo_mem[spi_sdo_rd_addr];
+  assign sdo_data = (sdo_source_select == SDO_SOURCE_STREAM) ?
+                     s_axis_sdo_data : sdo_mem[spi_sdo_rd_addr];
 
   /* SYNC ID counter. The offload module increments the sync_id on each
    * transaction. The initial value of the sync_id is the value of the last

diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -130,7 +130,7 @@ proc p_elaboration {} {
   if {[get_parameter_value SDO_STREAMING] != 1} {
     lappend disabled_intfs s_axis_sdo
   }
-  
+
   foreach intf $disabled_intfs {
     set_interface_property $intf ENABLED false
   }

diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

diff --git a/projects/ad57xx_ardz/Makefile b/projects/ad57xx_ardz/Makefile
@@ -4,4 +4,4 @@
 ## Auto-generated, do not modify!
 ####################################################################################
 
-include ../scripts/project-toplevel.mk
+include ../scripts/project-toplevel.mk
diff --git a/projects/ad57xx_ardz/Readme.md b/projects/ad57xx_ardz/Readme.md
@@ -30,4 +30,4 @@ hdl/projects/ad57xx_ardz/coraz7s> make
 ```
 hdl/projects/ad57xx_ardz> cd de10nano
 hdl/projects/ad57xx_ardz/de10nano> make
-```
+```
diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
@@ -18,10 +18,11 @@ set num_sdi       1
 set num_sdo       1
 set sdi_delay     0
 set echo_sclk     0
+set sdo_streaming 1
 
 set hier_spi_engine spi_ad57xx
 
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 
 # clkgen
 
@@ -44,7 +45,7 @@ ad_ip_parameter ad57xx_dma CONFIG.DMA_DATA_WIDTH_DEST $data_width
 # trigger generator
 
 ad_ip_instance axi_pwm_gen trig_gen
-ad_ip_parameter trig_gen CONFIG.N_PWMS 2
+ad_ip_parameter trig_gen CONFIG.N_PWMS 1
 ad_ip_parameter trig_gen CONFIG.PULSE_0_PERIOD 98
 ad_ip_parameter trig_gen CONFIG.PULSE_0_WIDTH 1
 

diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
@@ -92,16 +92,16 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 
 # exported interface
 
-add_interface ad57xx_spi_sclk       clock source
-add_interface ad57xx_spi_cs         conduit end
-add_interface ad57xx_spi_miso       conduit end
-add_interface ad57xx_spi_mosi       conduit end
-add_interface m_axis_offload_sdi    axi4stream end
-
-set_interface_property ad57xx_spi_cs    EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property ad57xx_spi_sclk  EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property ad57xx_spi_miso  EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property ad57xx_spi_mosi  EXPORT_OF spi_engine_execution_0.if_sdo
+add_interface ad57xx_spi_sclk    clock      source
+add_interface ad57xx_spi_cs      conduit    end
+add_interface ad57xx_spi_miso    conduit    end
+add_interface ad57xx_spi_mosi    conduit    end
+add_interface m_axis_offload_sdi axi4stream end
+
+set_interface_property ad57xx_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
+set_interface_property ad57xx_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
+set_interface_property ad57xx_spi_miso    EXPORT_OF spi_engine_execution_0.if_sdi
+set_interface_property ad57xx_spi_mosi    EXPORT_OF spi_engine_execution_0.if_sdo
 set_interface_property m_axis_offload_sdi EXPORT_OF spi_engine_offload_0.offload_sdi
 
 # clocks

diff --git a/projects/ad57xx_ardz/coraz7s/system_bd.tcl b/projects/ad57xx_ardz/coraz7s/system_bd.tcl
@@ -6,11 +6,6 @@
 source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
-adi_project_files ad57xx_ardz_coraz7s [list \
-  "$ad_hdl_dir/library/common/ad_edge_detect.v" \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"

diff --git a/projects/ad57xx_ardz/coraz7s/system_constr.xdc b/projects/ad57xx_ardz/coraz7s/system_constr.xdc
@@ -12,12 +12,12 @@ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad5
 set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_miso]
 set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_sclk]
 set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_syncb]
-set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_resetb ]
+set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_resetb]
 set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_ldacb]
 set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_clrb]
 
 # rename auto-generated clock for SPI Engine to spi_clk - 140MHz
-create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
+create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*axi_ad57xx_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*axi_ad57xx_clkgen*i_mmcm]]
 
 # create a generated clock for SCLK - fSCLK=spi_clk/4 - 35MHz
 create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -divide_by 4 [get_ports ad57xx_ardz_spi_sclk]
diff --git a/projects/ad57xx_ardz/coraz7s/system_top.v b/projects/ad57xx_ardz/coraz7s/system_top.v
@@ -103,28 +103,14 @@ module system_top (
     .dio_p(led));
 
   ad_iobuf #(
-    .DATA_WIDTH(1)
-  ) i_iobuf_ad57xx_ldacb_gpio (
-    .dio_t(gpio_t[34]),
-    .dio_i(gpio_o[34]),
-    .dio_o(gpio_i[34]),
-    .dio_p({ad57xx_ardz_ldacb}));
-
-  ad_iobuf #(
-    .DATA_WIDTH(1)
-  ) i_iobuf_ad57xx_clrb_gpio (
-    .dio_t(gpio_t[33]),
-    .dio_i(gpio_o[33]),
-    .dio_o(gpio_i[33]),
-    .dio_p({ad57xx_ardz_clrb}));
-
-  ad_iobuf #(
-    .DATA_WIDTH(1)
-  ) i_iobuf_ad57xx_resetb_gpio (
-    .dio_t(gpio_t[32]),
-    .dio_i(gpio_o[32]),
-    .dio_o(gpio_i[32]),
-    .dio_p({ad57xx_ardz_resetb}));
+    .DATA_WIDTH(3)
+  ) i_iobuf_ad57xx (
+    .dio_t(gpio_t[34:32]),
+    .dio_i(gpio_o[34:32]),
+    .dio_o(gpio_i[34:32]),
+    .dio_p({ad57xx_ardz_ldacb,
+            ad57xx_ardz_clrb,
+            ad57xx_ardz_resetb}));
 
   system_wrapper i_system_wrapper (
     .ddr_addr (ddr_addr),

diff --git a/projects/ad57xx_ardz/de10nano/Makefile b/projects/ad57xx_ardz/de10nano/Makefile
@@ -21,4 +21,4 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
 LIB_DEPS += spi_engine/spi_engine_offload
 LIB_DEPS += axi_pwm_gen
 
-include ../../scripts/project-intel.mk
+include ../../scripts/project-intel.mk
diff --git a/projects/ad57xx_ardz/de10nano/system_project.tcl b/projects/ad57xx_ardz/de10nano/system_project.tcl
@@ -32,7 +32,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_spi_miso
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_syncb
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_ldacb
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_clrb
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_resetb 
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad57xx_ardz_resetb
 
 # Arduino shield connections on de10_nano
 

diff --git a/projects/ad57xx_ardz/de10nano/system_qsys.tcl b/projects/ad57xx_ardz/de10nano/system_qsys.tcl
@@ -20,4 +20,4 @@ set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
 
 set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
 
-sysid_gen_sys_init_file;
+sysid_gen_sys_init_file;
diff --git a/projects/ad57xx_ardz/de10nano/system_top.v b/projects/ad57xx_ardz/de10nano/system_top.v
@@ -131,7 +131,6 @@ module system_top (
   wire             sys_resetn;
   wire    [63:0]   gpio_i;
   wire    [63:0]   gpio_o;
-  wire    [63:0]   gpio_t;
 
   wire             i2c1_out_sda;
   wire             i2c1_in_sda;
@@ -156,16 +155,17 @@ module system_top (
   assign gpio_bd_o[7:0] = gpio_o[7:0];
 
   // IO Buffers for EVAL-AD5781ARDZ I2C (EEPROM)
+
   ALT_IOBUF scl_eeprom_iobuf (
     .i(1'b0),
-    .oe(i2c1_out_sdl),
+    .oe(i2c1_out_scl),
     .o(i2c1_in_scl),
     .io(ad57xx_ardz_scl));
 
   ALT_IOBUF sda_eeprom_iobuf (
     .i(1'b0),
     .oe(i2c1_out_sda),
-    .o(i2c1_in_data),
+    .o(i2c1_in_sda),
     .io(ad57xx_ardz_sda));
 
   // IO Buffers for HDMI I2C
@@ -245,9 +245,9 @@ module system_top (
     .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
     .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
     .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n),
-    .sys_hps_i2c1_sda (i2c1_in_data),
+    .sys_hps_i2c1_sda (i2c1_in_sda),
     .sys_hps_i2c1_out_data (i2c1_out_sda),
-    .sys_hps_i2c1_clk_clk (i2c1_out_sdl),
+    .sys_hps_i2c1_clk_clk (i2c1_out_scl),
     .sys_hps_i2c1_scl_in_clk (i2c1_in_scl),
     .sys_gpio_bd_in_port (gpio_i[31:0]),
     .sys_gpio_bd_out_port (gpio_o[31:0]),
@@ -267,4 +267,4 @@ module system_top (
     .ad57xx_spi_miso_sdi(ad57xx_ardz_spi_miso),
     .ad57xx_spi_mosi_sdo(ad57xx_ardz_spi_mosi));
 
-endmodule
+endmodule