Skip to content

Commit

Permalink
adrv9026: Add vck190 support
Browse files Browse the repository at this point in the history 
Signed-off-by: AndrDragomir <[email protected]>
  • Loading branch information
@AndrDragomir
AndrDragomir committed Aug 29, 2024
1 parent 62720a5 commit e6c4bed
Show file tree
Hide file tree
Showing 7 changed files with 1,961 additions and 64 deletions.
303 changes: 239 additions & 64 deletions projects/adrv9026/common/adrv9026_bd.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,26 +3,61 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists ADI_PHY_SEL]} {
set ADI_PHY_SEL 1
}

if {![info exists INTF_CFG]} {
set INTF_CFG RXTX
}

if {![info exists TRANSCEIVER_TYPE]} {
set TRANSCEIVER_TYPE GTY
}

set JESD_MODE $ad_project_params(JESD_MODE)
set TX_LANE_RATE $ad_project_params(TX_LANE_RATE)
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)

set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS)
set RX_NUM_LINKS $ad_project_params(RX_NUM_LINKS)

set TX_JESD_L $ad_project_params(TX_JESD_L)
set TX_JESD_M $ad_project_params(TX_JESD_M)

set RX_JESD_L $ad_project_params(RX_JESD_L)
set RX_JESD_M $ad_project_params(RX_JESD_M)

# TX parameters
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] ; # L
set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP

set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)

# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] ; # L
set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP

set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)

set dac_fifo_name axi_adrv9026_dacfifo
set dac_data_width [expr 32*$TX_NUM_OF_LANES]
set dac_dma_data_width 128

if {$JESD_MODE == "8B10B"} {
set DATAPATH_WIDTH 4
set NP12_DATAPATH_WIDTH 6
set ENCODER_SEL 1
} else {
set DATAPATH_WIDTH 8
set NP12_DATAPATH_WIDTH 12
set ENCODER_SEL 2
}

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl

# adrv9026
Expand All @@ -31,15 +66,18 @@ create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I core_clk

# dac peripherals
if {$ADI_PHY_SEL == 1} {

ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
}

ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3

adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES
adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL

ad_ip_instance util_upack2 util_adrv9026_tx_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
Expand All @@ -66,17 +104,24 @@ ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32

ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width

if {$ADI_PHY_SEL == 1} {
# adc peripherals
ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
}
if {$ADI_PHY_SEL == 0} {
# reset generator
ad_ip_instance proc_sys_reset core_clk_rstgen
ad_connect core_clk core_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn core_clk_rstgen/ext_reset_in
}

ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3

adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES
adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL

ad_ip_instance util_cpack2 util_adrv9026_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
Expand All @@ -103,50 +148,145 @@ ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32

# common cores

ad_ip_instance util_adxcvr util_adrv9026_xcvr
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15

# xcvr interfaces

set tx_ref_clk tx_ref_clk_0
set rx_ref_clk rx_ref_clk_0

create_bd_port -dir I $tx_ref_clk
create_bd_port -dir I $rx_ref_clk
ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk

# Tx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {3 2 0 1} core_clk
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4

# Rx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch

# common cores
if {$ADI_PHY_SEL == 1} {
ad_ip_instance util_adxcvr util_adrv9026_xcvr
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
} else {
source ../common/versal_transceiver.tcl

set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
? $ad_project_params(REF_CLK_RATE) : 245.76 } ]

create_bd_port -dir I gt_reset
create_bd_port -dir O gt_powergood
create_bd_port -dir O rx_resetdone
create_bd_port -dir O tx_resetdone
create_bd_port -dir I gt_reset_rx_pll_and_datapath
create_bd_port -dir I gt_reset_tx_pll_and_datapath
create_bd_port -dir I gt_reset_rx_datapath
create_bd_port -dir I gt_reset_tx_datapath

switch $INTF_CFG {
"RXTX" {
create_versal_phy jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
set rx_phy jesd204_phy_rxtx
set tx_phy jesd204_phy_rxtx
ad_connect $rx_ref_clk ${rx_phy}/GT_REFCLK
ad_connect gt_reset ${rx_phy}/gtreset_in
ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk
ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn
ad_connect ${rx_phy}/gtpowergood gt_powergood
ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
ad_connect ${rx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
ad_connect ${tx_phy}/tx_resetdone tx_resetdone
}
"RX" {
create_versal_phy jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
set rx_phy jesd204_phy_rx
ad_connect $tx_ref_clk ${rx_phy}/GT_REFCLK
ad_connect gt_reset ${rx_phy}/gtreset_in
ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk
ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn
ad_connect ${rx_phy}/gtpowergood gt_powergood
ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
}
"TX" {
create_versal_phy jesd204_phy_tx $JESD_MODE $TX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
set tx_phy jesd204_phy_tx
ad_connect $ref_clock ${tx_phy}/GT_REFCLK
ad_connect gt_reset ${tx_phy}/gtreset_in
ad_connect $sys_cpu_clk ${tx_phy}/s_axi_clk
ad_connect $sys_cpu_resetn ${tx_phy}/s_axi_resetn
ad_connect ${tx_phy}/gtpowergood gt_powergood
ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
ad_connect ${tx_phy}/tx_resetdone tx_resetdone
}
}
}

if {$ADI_PHY_SEL == 1} {
ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk

# Tx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {3 2 0 1} {} core_clk
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4

# Rx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} {} core_clk
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
}
} else {
set rx_link_clock ${rx_phy}/rxusrclk_out
# Connect PHY to Link Layer
ad_connect axi_adrv9026_rx_jesd/rx_phy0 ${rx_phy}/rx1
ad_connect axi_adrv9026_rx_jesd/rx_phy1 ${rx_phy}/rx0
ad_connect axi_adrv9026_rx_jesd/rx_phy2 ${rx_phy}/rx2
ad_connect axi_adrv9026_rx_jesd/rx_phy3 ${rx_phy}/rx3

ad_connect $rx_link_clock /axi_adrv9026_rx_jesd/link_clk
ad_connect core_clk /axi_adrv9026_rx_jesd/device_clk
ad_connect axi_adrv9026_rx_jesd/phy_en_char_align ${rx_phy}/en_char_align

create_bd_port -dir I rx_sysref_0
ad_connect axi_adrv9026_rx_jesd/sysref rx_sysref_0

create_bd_port -dir O rx_sync_0
ad_connect rx_sync_0 axi_adrv9026_rx_jesd/sync

set tx_link_clock ${tx_phy}/txusrclk_out
# Connect PHY to Link Layer
ad_connect axi_adrv9026_tx_jesd/tx_phy0 ${tx_phy}/tx3
ad_connect axi_adrv9026_tx_jesd/tx_phy1 ${tx_phy}/tx2
ad_connect axi_adrv9026_tx_jesd/tx_phy2 ${tx_phy}/tx1
ad_connect axi_adrv9026_tx_jesd/tx_phy3 ${tx_phy}/tx0

ad_connect $tx_link_clock /axi_adrv9026_tx_jesd/link_clk
ad_connect core_clk /axi_adrv9026_tx_jesd/device_clk

create_bd_port -dir I tx_sysref_0
ad_connect axi_adrv9026_tx_jesd/sysref tx_sysref_0

create_bd_port -dir I tx_sync_0
ad_connect tx_sync_0 axi_adrv9026_tx_jesd/sync
}
# connections (dac)

ad_connect core_clk tx_adrv9026_tpl_core/link_clk
Expand Down Expand Up @@ -206,17 +346,21 @@ ad_connect util_adrv9026_rx_cpack/packed_sync axi_adrv9026_rx_dma/sync

ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
if {$ADI_PHY_SEL == 1} {
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
}
ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma

# gt uses hp0, and 100MHz clock for both DRP and AXI4

ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP0
if {$ADI_PHY_SEL == 1} {
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
}

# interconnect (mem/dac)

Expand All @@ -231,3 +375,34 @@ ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq

# Dummy outputs for unused lanes
if {$ADI_PHY_SEL == 1} {
if {$INTF_CFG != "TX"} {
# Unused Rx lanes
for {set i $RX_NUM_OF_LANES} {$i < 4} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
}
}
if {$INTF_CFG != "RX"} {
# Unused Tx lanes
for {set i $TX_NUM_OF_LANES} {$i < 4} {incr i} {
create_bd_port -dir O tx_data_${i}_n
create_bd_port -dir O tx_data_${i}_p
}
}
} else {
if {$INTF_CFG != "TX"} {
create_bd_port -dir I -from 3 -to 0 rx_0_p
create_bd_port -dir I -from 3 -to 0 rx_0_n
ad_connect rx_0_p ${rx_phy}/rx_0_p
ad_connect rx_0_n ${rx_phy}/rx_0_n
}
if {$INTF_CFG != "RX"} {
create_bd_port -dir O -from 3 -to 0 tx_0_p
create_bd_port -dir O -from 3 -to 0 tx_0_n
ad_connect tx_0_p ${rx_phy}/tx_0_p
ad_connect tx_0_n ${rx_phy}/tx_0_n
}
}
Loading

0 comments on commit e6c4bed

Please sign in to comment.