m2k, axi_dac_interpolate: Add auto rearm feature #1344
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AndreiGrozav
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PopPaul2021,
gastmaier and
sarpadi
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acostina
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Jun 14, 2024
This feature will allow the gating each buffer, cyclic included, by a trigger condition. Signed-off-by: AndreiGrozav <[email protected]>
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This commit fixes the last sample hold and spike before buffers at low samplerates by compensating for the interpolation filter delays. Signed-off-by: AndreiGrozav <[email protected]>
When the DAC is triggered from LA or ADC it can miss some trigger signals. This is because the trigger signal event can be active one clock cycle on the ADC clock domain, which drives both ADC and LA/PG. The ADC runs at 100MHz while the DAC runs at 75MHz. Previously the CDC logic was based simply on 2 FF sync stages. Because we we’re considering changing the DAC clock at 100MHz. This would have helped with reducing the delay on the DAC data path, also meaning reducing the delay between trigger and first samples getting out of the DAC. But because of harmonic consideration we stayed with 75MHz. This commit fixes the issue of missing the trigger signal on the DAC side. But, with introducing further delays on the trigger path. Also, because of the difference in sampling clocks, there will be a +/- one clock cycles uncertainty(75MHz) between clock launching and latching.
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This feature will allow the gating each buffer, cyclic ones included, by a trigger condition.
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