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Fix 58 typos in 15 files #2723

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Fix 58 typos in 15 files #2723

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2 changes: 1 addition & 1 deletion core/net/ip/uipopt.h
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Expand Up @@ -598,7 +598,7 @@ void uip_log(char *msg);
* \defgroup uipoptcpu CPU architecture configuration
* @{
*
* The CPU architecture configuration is where the endianess of the
* The CPU architecture configuration is where the endianness of the
* CPU on which uIP is to be run is specified. Most CPUs today are
* little endian, and the most notable exception are the Motorolas
* which are big endian. The BYTE_ORDER macro should be changed to
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10 changes: 5 additions & 5 deletions cpu/arm/aducrf101/Common/ADuCRF101.h
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Expand Up @@ -7375,11 +7375,11 @@ typedef struct { /*!< pADI_INTERRUPT Structure
/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */
#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 )

/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */
#define AIRCR_ENDIANESS_MSK (0x1 << 15 )
#define AIRCR_ENDIANESS (0x1 << 15 )
#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */
#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */
/* AIRCR[ENDIANNESS] - This bit is static or configured by a hardware input on reset */
#define AIRCR_ENDIANNESS_MSK (0x1 << 15 )
#define AIRCR_ENDIANNESS (0x1 << 15 )
#define AIRCR_ENDIANNESS_DIS (0x0 << 15 ) /* DIS */
#define AIRCR_ENDIANNESS_EN (0x1 << 15 ) /* EN */

/* AIRCR[PRIGROUP] - Priority grouping position */
#define AIRCR_PRIGROUP_MSK (0x7 << 8 )
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_cm0.h
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Expand Up @@ -450,8 +450,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_cm0plus.h
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Expand Up @@ -474,8 +474,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_cm3.h
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Expand Up @@ -505,8 +505,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_cm4.h
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Expand Up @@ -565,8 +565,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_cm7.h
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Expand Up @@ -609,8 +609,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_sc000.h
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Expand Up @@ -462,8 +462,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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4 changes: 2 additions & 2 deletions cpu/arm/common/CMSIS/core_sc300.h
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Expand Up @@ -502,8 +502,8 @@ typedef struct
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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2 changes: 1 addition & 1 deletion cpu/arm/common/SD-card/config.h
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Expand Up @@ -53,7 +53,7 @@
#define CLUSTER_PREALLOC_DIRECTORY 0


/* Endianess configuration
/* Endianness configuration
-----------------------

* Here you can configure wheter your architecture is little or big endian. This
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2 changes: 1 addition & 1 deletion cpu/arm/stm32f103/stm32f10x_map.h
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Expand Up @@ -2573,7 +2573,7 @@ typedef struct
#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */
#define SCB_AIRCR_ENDIANNESS ((u32)0x00008000) /* Data endianness bit */
#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */


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10 changes: 5 additions & 5 deletions cpu/arm/stm32l152/regs.h
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Expand Up @@ -9989,11 +9989,11 @@
#define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u)
#define SCS_AIRCR_VECTKEY_BIT (16)
#define SCS_AIRCR_VECTKEY_BITS (16)
/* ENDIANESS field */
#define SCS_AIRCR_ENDIANESS (0x00008000u)
#define SCS_AIRCR_ENDIANESS_MASK (0x00008000u)
#define SCS_AIRCR_ENDIANESS_BIT (15)
#define SCS_AIRCR_ENDIANESS_BITS (1)
/* ENDIANNESS field */
#define SCS_AIRCR_ENDIANNESS (0x00008000u)
#define SCS_AIRCR_ENDIANNESS_MASK (0x00008000u)
#define SCS_AIRCR_ENDIANNESS_BIT (15)
#define SCS_AIRCR_ENDIANNESS_BITS (1)
/* PRIGROUP field */
#define SCS_AIRCR_PRIGROUP (0x00000700u)
#define SCS_AIRCR_PRIGROUP_MASK (0x00000700u)
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10 changes: 5 additions & 5 deletions cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h
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Expand Up @@ -9959,11 +9959,11 @@
#define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u)
#define SCS_AIRCR_VECTKEY_BIT (16)
#define SCS_AIRCR_VECTKEY_BITS (16)
/* ENDIANESS field */
#define SCS_AIRCR_ENDIANESS (0x00008000u)
#define SCS_AIRCR_ENDIANESS_MASK (0x00008000u)
#define SCS_AIRCR_ENDIANESS_BIT (15)
#define SCS_AIRCR_ENDIANESS_BITS (1)
/* ENDIANNESS field */
#define SCS_AIRCR_ENDIANNESS (0x00008000u)
#define SCS_AIRCR_ENDIANNESS_MASK (0x00008000u)
#define SCS_AIRCR_ENDIANNESS_BIT (15)
#define SCS_AIRCR_ENDIANNESS_BITS (1)
/* PRIGROUP field */
#define SCS_AIRCR_PRIGROUP (0x00000700u)
#define SCS_AIRCR_PRIGROUP_MASK (0x00000700u)
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4 changes: 2 additions & 2 deletions tools/cooja/java/org/contikios/cooja/mote/memory/MemoryBuffer.java
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Expand Up @@ -34,7 +34,7 @@
/**
* Basic routines for memory access with multi-arch support.
*
* Handles endianess, integer size and address size.
* Handles endianness, integer size and address size.
*
* Supports padding/aligning.
*
Expand Down Expand Up @@ -85,7 +85,7 @@ public static MemoryBuffer wrap(MemoryLayout layout, byte[] array) {
*/
public static MemoryBuffer wrap(MemoryLayout layout, byte[] array, DataType[] structure) {
ByteBuffer b = ByteBuffer.wrap(array);
b.order(layout.order); // preset endianess
b.order(layout.order); // preset endianness
return new MemoryBuffer(layout, b, structure);
}

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6 changes: 3 additions & 3 deletions tools/cooja/java/org/contikios/cooja/mote/memory/MemoryLayout.java
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Expand Up @@ -32,7 +32,7 @@
import java.nio.ByteOrder;

/**
* Holds memory layout informations such as endianess, wordsize, C int size.
* Holds memory layout informations such as endianness, wordsize, C int size.
*
* @author Enrico Jorns
*/
Expand Down Expand Up @@ -174,13 +174,13 @@ public int getPaddingBytesFor(DataType currType, DataType nextType) {
/**
* Returns information string for this MemoryLayout.
*
* @return String that shows Endianess and word size.
* @return String that shows Endianness and word size.
*/
@Override
public String toString() {
StringBuilder sb = new StringBuilder();
return sb.append("MemoryLayout: ")
.append("Endianess: ").append(order)
.append("Endianness: ").append(order)
.append(", WORD_SIZE: ").append(WORD_SIZE)
.toString();
}
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