Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Replaced gavgpool with static_mean. #7202

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Replaced gavgpool with static_mean. #7202

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 0 additions & 1 deletion BUILD.bazel
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -219,7 +219,6 @@ MICROKERNEL_HDRS = [
"src/xnnpack/conv.h",
"src/xnnpack/dwconv.h",
"src/xnnpack/fill.h",
"src/xnnpack/gavgpool.h",
"src/xnnpack/gemm.h",
"src/xnnpack/ibilinear.h",
"src/xnnpack/igemm.h",
Expand Down
14 changes: 0 additions & 14 deletions CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -380,8 +380,6 @@ SET(OPERATOR_SRCS
src/operators/deconvolution-nhwc.c
src/operators/dynamic-fully-connected-nc.c
src/operators/fully-connected-nc.c
src/operators/global-average-pooling-ncw.c
src/operators/global-average-pooling-nwc.c
src/operators/lut-elementwise-nc.c
src/operators/max-pooling-nhwc.c
src/operators/prelu-nc.c
Expand Down Expand Up @@ -466,8 +464,6 @@ SET(XNNPACK_SRCS
src/configs/dwconv-config.c
src/configs/dwconv2d-chw-config.c
src/configs/experiments-config.c
src/configs/gavgpool-config.c
src/configs/gavgpool-cw-config.c
src/configs/gemm-config.c
src/configs/ibilinear-chw-config.c
src/configs/ibilinear-config.c
Expand Down Expand Up @@ -1447,8 +1443,6 @@ IF(XNNPACK_BUILD_TESTS)
f16-conv-hwc2chw
f16-f32acc-rdsum
f16-f32acc-rsum
f16-gavgpool-cw
f16-gavgpool-minmax
f16-ibilinear-chw
f16-ibilinear
f16-prelu
Expand All @@ -1460,8 +1454,6 @@ IF(XNNPACK_BUILD_TESTS)
f16-vmulcaddc-minmax
f32-conv-hwc
f32-conv-hwc2chw
f32-gavgpool-cw
f32-gavgpool-minmax
f32-ibilinear-chw
f32-ibilinear
f32-prelu
Expand All @@ -1479,17 +1471,13 @@ IF(XNNPACK_BUILD_TESTS)
f32-vscaleextexp
indirection
packing
qs8-gavgpool-minmax-fp32
qs8-gavgpool-minmax-rndnu
qs8-requantization
qs8-rdsum-minmax-fp32
qu8-rdsum
qs8-rsum
qu8-rsum
qs8-vhswish
qs8-vlrelu
qu8-gavgpool-minmax-fp32
qu8-gavgpool-minmax-rndnu
qu8-requantization
qu8-vhswish
qu8-vlrelu
Expand Down Expand Up @@ -1963,7 +1951,6 @@ IF(XNNPACK_BUILD_BENCHMARKS)
f16-f32acc-igemm
f16-f32acc-rdsum
f16-f32acc-rsum
f16-gavgpool-cw
f16-gemm
f16-gemm-minmax
f16-igemm
Expand All @@ -1979,7 +1966,6 @@ IF(XNNPACK_BUILD_BENCHMARKS)
f32-dwconv
f32-dwconv2d-chw
f32-f16-vcvt
f32-gavgpool-cw
f32-gemm
f32-gemm-goi-minmax
f32-gemm-minmax
Expand Down
2 changes: 0 additions & 2 deletions bench/BUILD.bazel
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -241,12 +241,10 @@ xnnpack_benchmark(
],
deps = MICROKERNEL_BENCHMARK_DEPS,
) for kernel in [
"f16_gavgpool_cw",
"f16_raddstoreexpminusmax",
"f16_rmax",
"f16_rminmax",
"f16_rmin",
"f32_gavgpool_cw",
"f32_raddexpminusmax",
"f32_raddextexp",
"f32_raddstoreexpminusmax",
Expand Down
77 changes: 0 additions & 77 deletions bench/f16-gavgpool-cw.cc
View file
Open in desktop

This file was deleted.

106 changes: 0 additions & 106 deletions bench/f32-gavgpool-cw.cc
View file
Open in desktop

This file was deleted.

4 changes: 0 additions & 4 deletions build_srcs.bzl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,6 @@ OPERATOR_SRCS = [
"src/operators/deconvolution-nhwc.c",
"src/operators/dynamic-fully-connected-nc.c",
"src/operators/fully-connected-nc.c",
"src/operators/global-average-pooling-ncw.c",
"src/operators/global-average-pooling-nwc.c",
"src/operators/lut-elementwise-nc.c",
"src/operators/max-pooling-nhwc.c",
"src/operators/prelu-nc.c",
Expand Down Expand Up @@ -112,8 +110,6 @@ XNNPACK_SRCS = [
"src/configs/conv-hwc2chw-config.c",
"src/configs/dwconv-config.c",
"src/configs/dwconv2d-chw-config.c",
"src/configs/gavgpool-config.c",
"src/configs/gavgpool-cw-config.c",
"src/configs/gemm-config.c",
"src/configs/ibilinear-chw-config.c",
"src/configs/ibilinear-config.c",
Expand Down
8 changes: 0 additions & 8 deletions cmake/gen/f16c_microkernels.cmake
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,6 @@ SET(PROD_F16C_MICROKERNEL_SRCS
src/f16-f32-vcvt/gen/f16-f32-vcvt-f16c-u16.c
src/f16-f32acc-rdsum/gen/f16-f32acc-rdsum-7p7x-f16c-c32.c
src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u32-acc4.c
src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c8.c
src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c8.c
src/f16-maxpool/f16-maxpool-9p8x-minmax-f16c-c8.c
src/f16-prelu/gen/f16-prelu-f16c-2x16.c
src/f16-rminmax/f16-rmax-f16c-u32.c
Expand Down Expand Up @@ -58,12 +56,6 @@ SET(NON_PROD_F16C_MICROKERNEL_SRCS
src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u16-acc2.c
src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u24-acc3.c
src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u32-acc2.c
src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c16.c
src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c24.c
src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c32.c
src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c16.c
src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c24.c
src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c32.c
src/f16-prelu/gen/f16-prelu-f16c-2x8.c
src/f16-vbinary/gen/f16-vadd-f16c-u8.c
src/f16-vbinary/gen/f16-vaddc-f16c-u8.c
Expand Down
35 changes: 0 additions & 35 deletions cmake/gen/neon_microkernels.cmake
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,6 @@ SET(PROD_NEON_MICROKERNEL_SRCS
src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4.c
src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4.c
src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-u8.c
src/f32-gavgpool-cw/f32-gavgpool-cw-neon-u4.c
src/f32-gavgpool/f32-gavgpool-7p7x-minmax-neon-c4.c
src/f32-gavgpool/f32-gavgpool-7x-minmax-neon-c4.c
src/f32-gemm/gen/f32-gemm-1x8-minmax-neon-lane-ld64.c
src/f32-gemm/gen/f32-gemm-4x2-minmax-neon-lane-ld64.c
src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-lane-ld128.c
Expand Down Expand Up @@ -99,8 +96,6 @@ SET(PROD_NEON_MICROKERNEL_SRCS
src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-rndnu-neon-mla8-ld64.c
src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mla8-ld64.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u32.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c8.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c8.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neon-mla8-ld128.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mla8-ld64.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neon-mla8-ld64.c
Expand All @@ -124,8 +119,6 @@ SET(PROD_NEON_MICROKERNEL_SRCS
src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-rndnu-neon-mul8.c
src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-rndnu-neon-mul8.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u32.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c8.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c8.c
src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-neon-mlal-lane.c
src/qu8-gemm/gen/qu8-gemm-1x16-minmax-rndnu-neon-mlal-lane.c
src/qu8-gemm/gen/qu8-gemm-3x8-minmax-rndnu-neon-mlal-lane.c
Expand Down Expand Up @@ -581,20 +574,6 @@ SET(NON_PROD_NEON_MICROKERNEL_SRCS
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u8.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u16.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u24.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c8.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c16.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c24.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c32.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c16.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c24.c
src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c32.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c8.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c16.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c24.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c32.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c16.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c24.c
src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-neon-mla8-ld64.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neon-mla8-ld64.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-4p8c-minmax-fp32-neon-mla8-ld64.c
Expand Down Expand Up @@ -802,20 +781,6 @@ SET(NON_PROD_NEON_MICROKERNEL_SRCS
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u8.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u16.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u24.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c8.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c16.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c24.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c32.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c16.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c24.c
src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c32.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c8.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c16.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c24.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c32.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c16.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c24.c
src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c32.c
src/qu8-gemm/gen/qu8-gemm-1x8-minmax-fp32-neon-mlal-lane.c
src/qu8-gemm/gen/qu8-gemm-1x16-minmax-fp32-neon-mlal-lane.c
src/qu8-gemm/gen/qu8-gemm-2x8-minmax-rndnu-neon-mlal-lane.c
Expand Down
Loading
Loading