Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Files reorganization #71

Draft
wants to merge 4 commits into
base: main
Choose a base branch
from
Draft
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
27 changes: 0 additions & 27 deletions Arm/Attr.lean

This file was deleted.

2 changes: 1 addition & 1 deletion Arm/Decode/BR.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel, Yan Peng
-/
import Arm.BitVec
import Data.BitVec

------------------------------------------------------------------------------

Expand Down
2 changes: 1 addition & 1 deletion Arm/Decode/DPI.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Arm.BitVec
import Data.BitVec

------------------------------------------------------------------------------

Expand Down
2 changes: 1 addition & 1 deletion Arm/Decode/DPR.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel, Yan Peng
-/
import Arm.BitVec
import Data.BitVec

------------------------------------------------------------------------------

Expand Down
2 changes: 1 addition & 1 deletion Arm/Decode/DPSFP.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Arm.BitVec
import Data.BitVec

------------------------------------------------------------------------------

Expand Down
2 changes: 1 addition & 1 deletion Arm/Decode/LDST.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel, Yan Peng
-/
import Arm.BitVec
import Data.BitVec

------------------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Exec.lean
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,6 @@ Copyright (c) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Arm.BitVec
import Arm.Decode
import Arm.Insts

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/BR/Compare_branch.lean
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace BR

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/BR/Cond_branch_imm.lean
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ Author(s): Yan Peng
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace BR

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/BR/Uncond_branch_imm.lean
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace BR

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/BR/Uncond_branch_reg.lean
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace BR

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/Common.lean
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ Author(s): Shilpi Goel, Yan Peng, Nathan Wetzler
-/

import LeanSAT
import Arm.BitVec
import Arm.State

section Common
Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPI/PC_rel_addressing.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace DPI

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPR/Conditional_select.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

namespace DPR

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_copy.lean
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ Author(s): Yan Peng

import Arm.Decode
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_extract.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_modified_immediate.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Yan Peng

import Arm.Decode
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_scalar_copy.lean
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ Author(s): Yan Peng

import Arm.Decode
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_three_same.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel, Yan Peng
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Advanced_simd_two_reg_misc.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Conversion_between_FP_and_Int.lean
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ Author(s): Yan Peng

import Arm.Decode
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Crypto_aes.lean
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ Author(s): Shilpi Goel, Yan Peng

import Arm.Decode
import Arm.Insts.Common
import Arm.BitVec
import Specs.AESCommon

----------------------------------------------------------------------
Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Crypto_four_reg.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel, Nevine Ebeid
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec

----------------------------------------------------------------------

Expand Down
1 change: 0 additions & 1 deletion Arm/Insts/DPSFP/Crypto_three_reg_sha512.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ Author(s): Shilpi Goel
import Arm.Decode
import Arm.State
import Arm.Insts.Common
import Arm.BitVec
import Specs.SHA512Common

----------------------------------------------------------------------
Expand Down
8 changes: 4 additions & 4 deletions Arm/State.lean
Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@ Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Lean.Data.Format
import Arm.BitVec
import Arm.Map
import Arm.Attr
import Arm.MinTheory
import Data.BitVec
import Data.Map
import Data.MinTheory
import Data.Attr

------------------------------------------------------------------------------
------------------------------------------------------------------------------
Expand Down
9 changes: 0 additions & 9 deletions Arm/Util.lean

This file was deleted.

73 changes: 0 additions & 73 deletions Arm/mem_separate_for_subset.smt2

This file was deleted.

9 changes: 9 additions & 0 deletions Data/Attr.lean
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
import Lean

-- A minimal theory, safe for all LNSym proofs
register_simp_attr minimal_theory
-- Non-interference lemmas for simplifying terms involving state
-- accessors and updaters.
register_simp_attr state_simp_rules
-- Rules for bitvector lemmas
register_simp_attr bitvec_rules
7 changes: 6 additions & 1 deletion Arm/BitVec.lean → Data/BitVec.lean
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ Author(s): Shilpi Goel

----------------------------------------------------------------------

import Arm.Attr
import Data.Attr

namespace BitVec

Expand Down Expand Up @@ -261,6 +261,11 @@ protected def flatten {n : Nat} (xs : List (BitVec n)) : BitVec (n * xs.length)
omega
BitVec.cast h (x ++ (BitVec.flatten rest))

/-- Reverse `x` and then flatten it. -/
def revflat (x : List (BitVec n)) : BitVec (n * x.length) :=
have h : n * x.reverse.length = n * x.length := by simp only [List.length_reverse]
BitVec.cast h $ BitVec.flatten (List.reverse x)

/-- Generate a random bitvector of width n. The range of the values
can also be specified using lo and hi arguments, which default to 0
and 2^n - 1 (inclusive), respectively. -/
Expand Down
File renamed without changes.
12 changes: 10 additions & 2 deletions Arm/MinTheory.lean → Data/MinTheory.lean
Original file line number Diff line number Diff line change
@@ -1,6 +1,14 @@
import Arm.Attr
/-
Copyright (c) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/

-- These lemmas are from lean/Init/SimpLemmas.lean.
-- A minimal theory, safe for all LNSym proofs

import Data.Attr

-- Source: lean/Init/SimpLemmas.lean.
attribute [minimal_theory] eq_self
attribute [minimal_theory] ne_eq
attribute [minimal_theory] ite_true
Expand Down
1 change: 0 additions & 1 deletion Proofs/Experiments/Max.lean
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@ Author(s): Shilpi Goel, Siddharth Bhat
The goal is to prove that this program implements max correctly.
-/
import Arm
import Arm.BitVec

namespace Max

Expand Down
1 change: 0 additions & 1 deletion Proofs/MultiInsts.lean
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Arm.Exec
import Arm.Util
import Tactics.Sym

namespace multi_insts_proofs
Expand Down
1 change: 0 additions & 1 deletion Proofs/Popcount32.lean
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Nathan Wetzler
-/
import Arm.Exec
import Arm.Util
import Tactics.Sym
import Tactics.StepThms

Expand Down
1 change: 0 additions & 1 deletion Proofs/SHA512/Sha512Sym.lean
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ Released under Apache 2.0 license as described in the file LICENSE.
Author(s): Shilpi Goel
-/
import Arm.Exec
import Arm.Util
import Tactics.Sym
import Proofs.SHA512.Sha512StepLemmas
import Lean
Expand Down
Loading