Change the soc from ace30_ptl to ace30

Renamed soc from ace30_ptl to ace30. We were previously using the wrong soc name. The correct name is ace30. There is only one ptl platform, but there can be several ace30 platforms. Signed-off-by: Grzegorz Bernat <[email protected]>
thesofproject · Sep 16, 2024 · 6c597ce · 6c597ce
1 parent 0df649a
commit 6c597ce
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Showing 6 changed files with 15 additions and 11 deletions.
diff --git a/app/sample.yaml b/app/sample.yaml
@@ -14,6 +14,7 @@ tests:
       - intel_adsp/cavs25
       - intel_adsp/ace15_mtpm
       - intel_adsp/ace20_lnl
+      - intel_adsp/ace30
       - intel_adsp/ace30_ptl
       - intel_adsp/ace30_ptl_sim
       - imx8qm_mek/mimx8qm6/adsp
@@ -25,6 +26,7 @@ tests:
       - intel_adsp/cavs25  # TGL
       - intel_adsp/ace15_mtpm  # MTL
       - intel_adsp/ace20_lnl
+      - intel_adsp/ace30
       - intel_adsp/ace30_ptl
       - intel_adsp/ace30_ptl_sim
       - imx8qm_mek/mimx8qm6/adsp

diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py
@@ -92,13 +92,13 @@ class PlatformConfig:
 # For instance: there's no open-source toolchain available for them yet.
 extra_platform_configs = {
 	"ptl" : PlatformConfig(
-		"intel", "intel_adsp/ace30_ptl",
+		"intel", "intel_adsp/ace30/ptl",
 		f"RI-2022.10{xtensa_tools_version_postfix}",
 		"ace30_LX7HiFi4_PIF",
 		ipc4 = True
 	),
 	"ptl-sim" : PlatformConfig(
-		"intel", "intel_adsp/ace30_ptl_sim",
+		"intel", "intel_adsp/ace30/ptl_sim",
 		f"RI-2022.10{xtensa_tools_version_postfix}",
 		"ace30_LX7HiFi4_PIF",
 		ipc4 = True

diff --git a/src/audio/base_fw_intel.c b/src/audio/base_fw_intel.c
@@ -64,7 +64,7 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data)
 	tuple = tlv_next(tuple);
 	tlv_value_uint32_set(tuple, IPC4_LP_EBB_COUNT_HW_CFG, PLATFORM_LPSRAM_EBB_COUNT);
 
-#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+#ifdef CONFIG_SOC_INTEL_ACE30
 	tuple = tlv_next(tuple);
 	tlv_value_uint32_set(tuple, IPC4_I2S_CAPS_HW_CFG, I2S_VER_30_PTL);
 #endif

diff --git a/west.yml b/west.yml
@@ -11,6 +11,8 @@ manifest:
       url-base: https://github.com/thesofproject
     - name: zephyrproject
       url-base: https://github.com/zephyrproject-rtos
+    - name: gbernatxintel
+      url-base: https://github.com/gbernatxintel
 
   # When upgrading projects here please run git log --oneline in the
   # project and if not too long then include the output in your commit
@@ -43,8 +45,8 @@ manifest:
 
     - name: zephyr
       repo-path: zephyr
-      revision: 689d1edee1d57f052b1d4572d67618c0b0e2b8a4
-      remote: zephyrproject
+      revision: gb_ptl_to_ace_3
+      remote: gbernatxintel
 
       # Import some projects listed in zephyr/west.yml@revision
       #

diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
@@ -242,7 +242,7 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 			${SOF_PLATFORM_PATH}/lunarlake/lib/clk.c
 		)
 
-	zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL
+	zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30
 			${SOF_PLATFORM_PATH}/pantherlake/lib/clk.c
 		)
 
@@ -272,7 +272,7 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 		set(PLATFORM "meteorlake")
 	elseif(CONFIG_SOC_INTEL_ACE20_LNL)
 		set(PLATFORM "lunarlake")
-	elseif(CONFIG_SOC_INTEL_ACE30_PTL)
+	elseif(CONFIG_SOC_INTEL_ACE30)
 		set(PLATFORM "pantherlake")
 	endif()
 

diff --git a/zephyr/lib/dma.c b/zephyr/lib/dma.c
@@ -78,12 +78,12 @@ SHARED_DATA struct dma dma[] = {
 	.plat_data = {
 		.dir		= DMA_DIR_DEV_TO_MEM,
 		.caps		= DMA_CAP_HDA,
-#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
 		.devs		= DMA_DEV_HDA | DMA_DEV_SSP |
 					  DMA_DEV_DMIC | DMA_DEV_ALH,
 #else
 		.devs		= DMA_DEV_HDA,
-#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */
+#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */
 		.channels	= DT_PROP(DT_NODELABEL(hda_link_in), dma_channels),
 		.period_count	= HDA_DMA_BUFFER_PERIOD_COUNT,
 	},
@@ -95,12 +95,12 @@ SHARED_DATA struct dma dma[] = {
 	.plat_data = {
 		.dir		= DMA_DIR_MEM_TO_DEV,
 		.caps		= DMA_CAP_HDA,
-#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
 		.devs		= DMA_DEV_HDA | DMA_DEV_SSP |
 					  DMA_DEV_DMIC | DMA_DEV_ALH,
 #else
 		.devs		= DMA_DEV_HDA,
-#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */
+#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */
 		.channels	= DT_PROP(DT_NODELABEL(hda_link_out), dma_channels),
 		.period_count	= HDA_DMA_BUFFER_PERIOD_COUNT,
 	},